參數(shù)資料
型號(hào): STP20N06
廠商: 意法半導(dǎo)體
英文描述: N - CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR
中文描述: ? -通道增強(qiáng)型功率MOS器件
文件頁(yè)數(shù): 12/20頁(yè)
文件大?。?/td> 221K
代理商: STP20N06
12
STP2000QFP
32-bit SBus Master I/O Controller
Master I/O
July 1997
1. These minimum numbers are required to comply with ANSI SCSI spec. For Synchronous SCSI data transfers and FASTCLK enabled,
the clock inputs must also meet the following requirements: 2t
CP
+ t
CL
> 97.92 ns and 2t
CP
+ t
CH
> 97.92 ns.
Synchronous SCSI Input Cycle
42
Data setup to SCSI_REQ/SCSI_ACK low
5
ns
43
Data hold from SCSI_REQ/SCSI_ACK low
15
ns
44
SCSI_REQ assertion period
27
ns
45
SCSI_REQ negation period
20
ns
46
SCSI_ACK assertion period
20
ns
47
SCSI_ACK negation period
20
ns
AC Characteristics: Ethernet Timing
Signal #
Parameter
Min
Max
Units
48
ENET_TCLK period
99
101
ns
49
ENET_TCLK high pulse duration
45
ns
50
ENET_TCLK low pulse duration
45
ns
51
ENET_TCLK rise time
8
ns
52
ENET_TCLK fall time
8
ns
53
ENET_TENA propagation delay after rising edge of ENET_TCLK
25
ns
54
ENET_TENA hold time after ENET_TCLK rising
7
ns
55
ENET_TX propagation delay after ENET_TCLK rising
32
ns
56
ENET_TX hold time after ENET_TCLK rising
7
ns
57
ENET_RCLK period
85
118
ns
58
ENET_RCLK high pulse duration
38
ns
59
ENET_RCLK low pulse duration
38
ns
60
ENET_RCLK rise time
8
ns
61
ENET_RCLK fall time
8
ns
62
ENET_RX data rise time
8
ns
63
ENET_RX data fall time
8
ns
64
ENET_RX data hold time from ENET_RCLK rising
5
ns
65
ENET_RX data setup time to ENET_RCLK rising
40
ns
66
ENET_RENA low duration
120
ns
67
ENET_CLSN high duration
110
ns
68
ENET_RENA hold time after the rising edge of ENET_RCLK
1
ns
69
ENET_RENA defer before ENET_TENA
356
ns
70
ENET_RENA extended after ENET_RCLK last falling
275
ns
AC Characteristics: SCSI TIming (Continued)
Signal #
Parameter
Conditions
Min
Max
Units
This Material Copyrighted by Its Respective Manufacturer
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