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參數(shù)資料
| 型號： | STK11C88-3W45 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 32K X 8 NVSRAM 3.3 V QUANTUM TRAP CMOS NONVOLATILE STATIC RAM |
| 中文描述： | 32K的× 8非易失性SRAM 3.3伏量子端粒酶的CMOS非易失靜態(tài)RAM |
| 文件頁數(shù)： | 8/9頁 |
| 文件大小： | 90K |
| 代理商： | STK11C88-3W45 |
STK11C88-3
July 1999
5-18
Internally,
RECALL
is a two-step procedure. First,
the
SRAM
data is cleared, and second, the nonvola-
tile information is transferred into the
SRAM
cells.
After the t
RECALL
cycle time the
SRAM
will once again
be ready for
READ
and
WRITE
operations. The
RECALL
operation in no way alters the data in the
EEPROM
cells. The nonvolatile data can be recalled
an unlimited number of times.
POWER-UP
RECALL
During power up, or after any low-power condition
(V
CC
< V
RESET
), an internal
RECALL
request will be
latched. When V
CC
once again exceeds the sense
voltage of V
SWITCH
, a
RECALL
cycle will automatically
be initiated and will take t
RESTORE
to complete.
If the STK11C88-3 is in a
WRITE
state at the end of
power-up
RECALL
, the
SRAM
data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
V
CC
or between E and system V
CC
.
HARDWARE PROTECT
The STK11C88-3 offers hardware protection
against inadvertent
STORE
operation during low-
voltage conditions. When V
CC
< V
SWITCH
, all software
STORE
operations are inhibited.
LOW AVERAGE ACTIVE POWER
The STK11C88-3 draws significantly less current
when it is cycled at times longer than 55ns. Figure 2
shows the relationship between I
CC
and
READ
cycle
time. Worst-case current consumption is shown for
both
CMOS
and
TTL
input levels (commercial tem-
perature range, V
CC
= 3.6V, 100% duty cycle on
chip enable). Figure 3 shows the same relationship
for
WRITE
cycles.If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK11C88-3 depends on the following
items: 1)
CMOS
vs.
TTL
input levels; 2) the duty
cycle of chip enable; 3) the overall cycle rate for
accesses; 4) the ratio of
READ
s to
WRITE
s; 5) the
operating temperature; 6) the V
CC
level; and 7) I/O
loading.
Figure 2: I
CC
(max) Reads
0
10
20
30
40
50
50
100
Cycle Time (ns)
150
200
TTL
CMOS
A
Figure 3: I
CC
(max) Writes
0
10
20
30
40
50
50
100
Cycle Time (ns)
150
200
TTL
CMOS
A
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| STK11C88-3W45I | 制造商:SIMTEK 制造商全稱:Simtek Corporation 功能描述:32K x 8 nvSRAM 3.3V QuantumTrap⑩ CMOS Nonvolatile Static RAM |
| STK11C88-3W55 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32K X 8 NVSRAM 3.3 V QUANTUM TRAP CMOS NONVOLATILE STATIC RAM |
| STK11C88-3W55I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32K X 8 NVSRAM 3.3 V QUANTUM TRAP CMOS NONVOLATILE STATIC RAM |
| STK11C88-3WF25 | 制造商:SIMTEK 制造商全稱:Simtek Corporation 功能描述:32K x 8 nvSRAM 3.3V QuantumTrap⑩ CMOS Nonvolatile Static RAM |
| STK11C88-3WF25I | 制造商:SIMTEK 制造商全稱:Simtek Corporation 功能描述:32K x 8 nvSRAM 3.3V QuantumTrap⑩ CMOS Nonvolatile Static RAM |
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