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STD150
iv
Samsung ASIC
Contents
Contents
1
Introduction
1.1 Library Description................................................................................................................1-1
1.2 Features................................................................................................................................1-2
1.3 EDA Support .........................................................................................................................1-4
1.4 Product Family ......................................................................................................................1-4
1.4.1 Analog Core Cell.................................................................................................1-4
1.4.2 Standard Logic Cells...........................................................................................1-8
1.4.3 Compiled Macrocells...........................................................................................1-9
1.4.4 Input/Output Cells ...............................................................................................1-11
1.5 Timings..................................................................................................................................1-13
1.6
Design for Test (DFT) Methodology......................................................................................1-22
1.7
Maximum Fanouts................................................................................................................1-25
1.8
Packages Capability by Pitch and Lead Count.....................................................................1-31
1.9
Power Dissipation.................................................................................................................1-32
1.10 Crystal Oscillator Considerations .........................................................................................1-36
2
Electrical Characteristics
DC Electrical Characteristics.........................................................................................................2-1
3
Internal Macrocells
Overview .......................................................................................................................................3-1
Summary Tables ...........................................................................................................................3-2
Logic Cells
AD2/AD2D2/AD2D4/AD2D8 .........................................................................................................3-15
AD2B/AD2BD2/AD2BD4/AD2BD8................................................................................................3-17
AD3/AD3D2/AD3D4......................................................................................................................3-19
AD4/AD4D2/AD4D4......................................................................................................................3-21
AD5/AD5D2/AD5D4......................................................................................................................3-23
ND2/ND2D2/ND2D4/ND2D8.........................................................................................................3-26
ND2B/ND2BD2/ND2BD4/ND2BD8...............................................................................................3-28
ND3/ND3D2/ND3D4 .....................................................................................................................3-30
ND3B/ND3BD2/ND3BD4/ND2BD8...............................................................................................3-33
ND4/ND4D2/ND4D4 .....................................................................................................................3-36
ND5/ND5D2/ND5D4 .....................................................................................................................3-38