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Introduction
1.1 Library Description
Samsung ASIC
1-1
STD150
1.1
Library
Description
STD150 is Samsung's next generation Standard Cell library containing standard
cells implemented in Samsung's 0.13
μ
m, L13G process technology. Samsung's
L13G process uses 4 to 7 metal interconnect layers. The STD150 library contains
diverse application specific digital and analog IP for System-on-Chip (SoC)
applications. Samsung provides a full range of cells within the STD150 library to
address the challenges of designing and producing ultra low power as well as
high density devices that take advantage of SoC integration. With its reduced
power dissipation and high density, STD150 can help reduce system cost for high
performance applications such as HDD, Networking, and Displays.
STD150 library supports gate counts of up to 46 million gates with 85% usability.
Gate delay is 20% faster than that of STD130, 0.18
μ
m library. Logic and compiled
memory density are twice denser than those of STD130, respectively.
STD150 supports also fully user configurable memories suitable for high-density
or low-power applications. To get much higher yield for SoC designs, it contains
the repairable memory with row redundant elements for high-capacity memory.
STD150 library also supports a wide range of I/O interface voltages and
standards. I/O cells that drive 2.5V, and 3.3V are available as 5V tolerant I/Os.
Available I/O standards include LVTTL, LVCMOS, PCI, PCI-X, OSC, AGP,
PECL, HSTL, SSTL2, GTLp, LVDS.
To better support SoC design, a robust collection of digital and analog IP cores
are available. Digital cores include the ARM7TDMI, ARM9TDMI, ARM920T,
ARM940T, ARM946E-S, and ARM926E-JS from ARM Ltd., as well as the Teak
and TeakLite DSP cores from the DSP Group. Analog cores include ADCs,
DACs, CODECs, and PLLs with various bit configurations and frequency ranges.
A thick oxide process option allows for high resolution operation of analog cores
with a 3.3V power supply.
In addition, the STD150 library supports communication and data transmission
cores such as, IEEE1284, IEEE1394 link controller, UART, PCI controller,
PCMCIA controller and 10/100 ethernet MAC.
Samsung's design methodology offers a comprehensive timing driven design
flow including automated time budgeting, tight floor plan synthesis integration,
powerful timinganalysis, and timing driven layout. Our advanced characterization
flow provides accurate timing data and robust delay models for L13G, our 0.13
μ
m
very deep sub-micron process technology. Static verification methods, such as
static timing analysis and formal equivalence checking, provide an effective
verification methodology with a variety of simulators. Samsung's Design-for-Test
(DFT) methodology supports full and partial scan chain design, BIST, JTAG
boundary scan, and Built-in-Redundancy-Analysis (BIRA) for reparable SRAM.
Samsung provides a full set of test ready IP cores with an efficient core test
integration methodology.