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1.4 Product Family
Introduction
STD150
1-10
Samsung ASIC
All of compiled memories provide edge-triggered synchronous read and write
operations, bit-write or byte write capability, and zero hold time for data-in,
addresses and control pins. Fully static design provides low-voltage data
retention and zero standby current. In case of multi-port register file, 2-port(1-
read/1-writ), 3-port(2-read/1-write) and 4-port(2-read/2-write) are available.
As speciality memory, two types of memories are supported by customer’s
requirements: Synchronous First-In First-Out Memory (FIFO) and synchronous
Content Addressable Memory with Binary state (CAM). FIFO, which is widely
usedincommunicationbufferingtypesofapplications,hasalsofullysynchronous
operation at the rising-edge of clock. CAM, which is useful in many applications
such as cache tag tables and translation look-up table buffers, has also fully
synchronous operation at the rising-edge of clock. Additional information about
the above speciality memory can be obtained from your local Samsung and
Design Center or Samsung’s worldwide headquarters.
In SoC(System-On-Chip) design, memory becomes much more dominant and
larger memory is required. To support it, the high-capacity memory, which covers
from 2M-bit to 4M-bit, is provided as the user-configurable compiler: High-
Capacity Single-Port Synchronous SRAM with Burst features (HCSPSRAM) and
High-Capacity Single-Port Synchronous Via-1Programmable ROM (HCVROM).
HCSPSRAM contains both Row-Redundancy and Column-Redundancy
schemes to guarantee higher yield and provides 4 burst-read and burst-write
operations suitable for cache applications. HCVROM is via-1 programmable and
istargetedforhigh-densityapplicationswithlowerpowerconsumption.HCVROM
can be easily extended to up to 4Mbits. Those memories will be also supported
by customer’s requirements. Additional information can be obtained from your
local Samsung and Design Center or Samsung’s worldwide headquarters.
Built-In-Self-Test (BIST) circuitry is available for most of STD150 compiled
memories. BIST circuits are designed to detect a set of fault types that impact the
functionality of memory and is generated by a softmacro-based BIST generator.
The softmacro-based BIST generator generates either an individual BIST netlist
for each memory or a shared BIST netlist for all memories use in a design.
However, when several memories of the same or the different type area used in
the design, if you generate the individual BIST netlist for each memory, there are
some redundant blocks because the individual BIST netlist has same function. In
this case, it would better use the shared BIST netlist to eliminate such
redundancies. In case of the compiled memory with redundancy, it supports Built-
In-Redundancy-Analysis (BIRA) to repair failed bits.