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Samsung ASIC
5-65
STD150
DPSRAMR_HD
High-Density Dual-Port Synchronous Static RAM with Redundancy
Application Notes
1.
Permitting Over-the-cell routing. In chip-level layout, over-the-cell routing in DPSRAMR_HD is
permitted for Metal-5 layer or upper layers.
2.
Incoming power bus should be adjusted to guarantee NOT more than 10% voltage drop at typical-case
current levels.
3.
Power stripe should be tapped from both sides of DPSRAMR_HD.
4.
Contention mode in same address access. In DPSRAMR_HD, simultaneous operation by both ports
on the same memory address, as write/write, write/read or read/write operation, causes a contention
problem. Simultaneous operation is defined as a state in which both ports are enabled, both address
buses are equal at the rising edge of CK. DPSRAMR_HD has no scheme preventing the contention.
Due to simultaneous operation, silicon will behave unpredictably. A write operation cannot end and data
appearing at outputs may not be valid. Please refer to the timing diagrams if you want to avoid the
contention mode between both ports. In write/write operation, the data stored at the current address will
be unpredictable. In write/read or read/write operation, the read port is invalid while the write port is still
valid. If you want to avoid the contention mode, you have to give the value greater than tcc
(clock-to-clock setup time). However, simultaneous read/read is allowable without any restrictions.
5.
A byte-write or word-write operation with DPSRAMR_HD. Refer to the function table. In byte-write
operation, the number of BWEN[] signal bus should be divided by a byte (8) and eight BWEN signals
should be tied to a connection wire. In this case, DI[] bus is controlled by a byte-wired BWEN signal
instead of each BWEN bit. In word-write operation, the functionality is exactly same as DPSRAM_HD. If
all of BWEN[] signal is tied to low state, DI[] bus is only controlled by WEN.