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STD150
5-28
Samsung ASIC
SPSRAMR_HD
High-Density Single-Port Synchronous Static RAM with Redundancy
Logic Symbol
Function Description
SPSRAMR_HD is a repairable single-port synchronous static RAM with bit-write capability which is provided
as a compiler. SPSRAMR_HD is intended for use in high-capacity applications. Basically, its functionality is
exactly same as SPSRAMBW_HD. Each bit of BWEN[] enables or disables the write operation of its
corresponding bit in DI[]. On the rising edge of CK, the write cycle is initiated when WEN is low and CSN is
low. When the individual bit of BWEN[] is low, the data on the corresponding write data bit of DI[] are written
into the memory location specified on A[]. When all bits of BWEN[] are high, any data in DI[] are not written
into the memory location specified on A[]. When all bits of BWEN[] are low, the data in DI[] are written into
the memory location specified on A[], which is exactly same as the write operation in SPSRAM_HD. During
the write cycle, DOUT[] remains stable. On the rising edge of CK, the read cycle is initiated when WEN is
high and CSN is low. The data at DOUT[] become valid after a delay. While in standby mode that CSN is
high, A[] and DI[] are disabled, data stored in the memory is retained and DOUT[] remains stable. When
OEN is high, DOUT[] is placed in a high-impedance state.
SPSRAMR_HD Function Table
CK
X
X
↑
↑
↑
↑
CSN
X
H
L
L
L
L
WEN
X
X
L
L
L
H
OEN
H
L
L
L
L
L
A
X
X
BWEN
X
X
all L
L/H
all H
X
DI
X
X
DOUT
Z
DOUT(t-1)
DOUT(t-1)
DOUT(t-1)
DOUT(t-1)
MEM(A)
Comment
Unconditional tri-state output
De-selected (standby mode)
Word-write cycle
Bit-write cycle
No operation
Read cycle
Valid
Valid
Valid
Valid
Valid
Valid
Valid
X
Features
High-capacity application
Heuristic row-redundancy available
Bit-write capability
Separated data I/O
Synchronous operation
Duty-free clock cycle
Asynchronous tri-state output control
Latched inputs and outputs
Automatic power-down
Near zero hold time
Low noise output optimization
Flexible aspect ratio
Dual-bank scheme available
64Kbits ~ 1Mbits capacity
2K ~ 32K number of words
8 ~ 128 number of bits per word
NOTES:
1. Words (w) is the number of words.
2. Bpw (b) is the number of bits per word.
3. Ymux (y) is one of the column mux types.
4. Banks(ba) is the number of banks.
5. m =
log
2
w
CK
CSN
WEN
spsramr_hd_<w>x<b>m<y>b<ba>
DOUT [b-1:0]
OEN
A [m-1:0]
DI [b-1:0]
BWEN[b-1:0]