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COMPILED MEMORY
OVERVIEW
Samsung ASIC
5-1
STD150
OVERVIEW
This section is an overview of STD150 compiled memories. STD150 compiled memories provide
application-specific memory solution – high-density and low-power applications. That is, two different
compiled memory libraries are available in STD150: High-Density compiled memory and Low-Power
compiled memory.
The high-density compiled memories are suitable for high-integration application. The low-power compiled
memories are suitable for portable applications. Each of these memory types may be customized to satisfy
the specific circuit requirements. Each memory uses state-of-the-art design architecture techniques such as
automatic power-down techniques, advanced partial activations and process-insensitive circuit designs. The
final memory block is implemented as a stand-alone, pitch-matched and customized leafcells. The compiled
memory is fully generated by Samsung’s memory compiler, called CubicCompiler as a user-configurable
compiler. The user defines the memory-related specifications such as word depth, bit per word, column mux
type and so on. The compiler then produces any or all of the following items:
— Complete functional model for simulation
— Tabular model for timing and power characteristics
— Automatic generated datasheet including all information for specific memory configuration
— Full GDS and schematic netlist for layout verification
— Phantom cell to use in chip-level floor planning and layout
Additional information about compiled memories can be obtained from your local Samsung and Design
Center or Samsung’s worldwide headquarters.
COMPILED MEMORY NAMING CONVENTION
In this chapter, we describe the naming convention of memory. The memory name, Figure 5-1 consists of
the following convention.
Figure 5-1. Compiled Memory Naming Convention
The first string, ‘
memory_code
’, means the name of memory type. In STD150 compiled memory, the
available memory types are as follows :
— SPSRAM
— SPSRAMBW
— SPSRAMR
— DPSRAM
— DPSRAMBW
— VROM
— SRFRAM
— SRFRAMBW
— FIFO
*
— CAM
*
— HCSPSRAM
*
: Single-Port Synchronous SRAM
: Single-Port Synchronous SRAM with Bit-Write
: Single-Port Synchronous SRAM with Redundancy
: Dual-Port Synchronous SRAM
: Dual-Port Synchronous SRAM with Bit-Write
: Synchronous Via-1 Programmable ROM
: Multi-Port Synchronous Register File
: Multi-Port Synchronous Register File with Bit-Write
: Synchronous First-In First-Out Memory
: Synchronous Content Addressable Memory
: High-Capacity Single-Port Synchronous SRAM with Burst features
‘memory_name’:= [memory_code]_[appl_code]_[procs_code]_[opt_code]_[config_code]