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Samsung ASIC
5-227
STD130
SPARAMBW_LP
Low-Power Single-Port Asynchronous Static RAM with Bit-Write
Logic Symbol
Function Description
SPARAMBW_LP is a single-port asynchronous static RAM with bit-write capability which is provided as a
compiler. SPARAMBW_LP is intended for use in Low-Power applications. Basically, its functionality is
exactly same as SPARAM_LP except a bit-write operation which is controlled by BWEN[], named bit-write
enable signal bus. Each bit of BWEN[] enables or disables the write operation of its corresponding bit in DI[].
At the falling edge of WEN, the write cycle is initiated when CSN is low. The data bits in DI[], which their
corresponding bit(s) in BWEN[] are low, are written into the memory location specified on A[]. When all bits
of BWEN[] are high, any data in DI[] are not written into the memory location specified on A[]. When all bits
of BWEN[] are low, the data in DI[] are written into the memory location specified on A[], which is exactly
same as the write operation in SPARAM_LP. At the rising edge of WEN, the write cycle is ended. The read
cycle is initiated when WEN is high and CSN is low. The data at DOUT[] become valid after a delay
whenever A[] transition is detected. While in standby mode that CSN is high, A[] and DI[] are disabled, data
stored in the memory is retained and DOUT[] remains stable. When OEN is high, DOUT[] is placed in a
high-impedance state.
SPARAMBW_LP Function Table
CSN
X
H
L
L
L
L
L
L
L
WEN
X
X
↓
↓
↑
↑
L
L
H
OEN
H
L
L
L
L
L
L
L
L
A
X
X
BWEN
X
X
all L
L
all L
L
all L
L
X
DI
X
X
DOUT
Z
DOUT(t-1)
DOUT(t-1)
DOUT(t-1)
MEM(A)
MEM(A)
DOUT(t-1)
DOUT(t-1)
MEM(A)
Comment
Unconditional tri-state output
De-selected (standby mode)
Word-write cycle starts
Bit-write cycle starts
Word-write cycle ends and read cycle starts
Bit-write cycle ends and read cycle starts
Word-write cycle
Bit-write cycle
Read cycle
Valid
Valid
Valid
Valid
Stable
Stable
Toggle
Valid
Valid
Valid
Valid
Valid
Valid
X
Features
Suitable for low-power application
Bit-Write capability
Separated data I/O
Asynchronous operation
Asynchronous tri-state output
Address transition detector
Write-enable transition detector
Chip-select transition detector
Automatic power-down mode available
Low noise output optimization
Zero standby current
Zero hold time for Data-In and BWEN
Flexible aspect ratio
Up to 512K bits capacity
Up to 16K number of words
Up to 256 number of bits per word
CSN
WEN
OEN
A [m-1:0]
DI [b-1:0]
sparambw_lp_<w>x<b>m<y>
DOUT [b-1:0]
NOTES:
1. Words (w) is the number of words.
2. Bpw (b) is the number of bits per word.
3. Ymux (y) is one of the column mux types.
4. m =
log
2
w
BWEN [b-1:0]