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1.10 VDD/VSS Rules And Guidelines
Introduction
STD130
1-36
Samsung ASIC
1.10
V
DD
/V
SS
Rules
And Guidelines
Three kinds of power supplies exist in STD130 providing power to internal and
I/O areas:
Core logic
– VDD1I, VSS1I
Pre-driver (I/O area)
– VDD3P, VDD2P, VDD1P, VSS3P, VSS2P, VSS1P
Output-drive (I/O area)
– VDD3O, VDD2O, VDD1O, VSS3O, VSS2O, VSS1O
The number of V
DD
and V
SS
pads required for a specific design depends on the
following factors:
Number of input and output buffers
Number of simultaneous switching outputs
Number of used gates and simultaneous switching gates
Operating frequency
1.10.1 BASIC PLACEMENT GUIDELINES
The purpose of these guidelines is to minimize IR drop and noise for reliable
device operations.
Core logic and pre-driver V
DD
/V
SS
pads should be evenly distributed on all
sides of the chip.
If you have core block demanding high power (compiled memory, analog),
extra power pads should be used to supply that block.
Power pads for SSO group should be evenly distributed in the SSO group.
Do not place the quiet signal (analog, reference), analog power (VDDA/
VSSA), or bi-directional buffer next to a SSO group.
Opposite types of power pads (V
DD
/V
SS
) should be placed as close together
as possible.
If possible, do not place power pads (V
DD
/V
SS
) at the corner of the chip.
1.10.2 VDD1I/VSS1I ALLOCATION GUIDELINES
The purpose of these guidelines is to ensure that the minimum number of core
logic power pad pairs are used while meeting the electromigration rules. The
number of VDD1I/VSS1I pads required for a specific design is a function of the
operating frequency of a chip.
VDD1I bus width and the number of pads are equal to those of VSS1I
VDD1I/VSS1I buses and pads should be distributed evenly in the core and
on each side of the chip.