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Introduction
1.6 Design for Test (DFT) Methodology
Samsung ASIC
1-23
STD130
The ASIC designer is free to fill in the version and part number in any manner as
long as all twenty bits are used.
Samsung’s JEDEC code: 78 decimal = 1001110
Continuation field (4 bits) = 0000
Contents of device identification register:
XXXX XXXXXXXXXXXXXXXX 0000 1001110 1
Users can define these two fields.
Test Data Registers Description
Bypass register: The bypass register provides a single-bit serial connection through the circuit when none of
the other test data registers are selected. It can be used to allow test data to flow through a given
device to the other components in a product without affecting a normal operation.
Boundary scan register: The boundary scan register detects typical production defects in board
interconnects, such as opens, and shorts. It also allows access to component inputs and outputs when
testing their logic or sample flow-through signals. Special boundary scan register macrocells are
provided for this purpose.
Design-specific test data register: These optional registers may be provided to allow access to design-
specific test support features in the integrated circuit, such as self-test and scan test.
Device identification register: This is an optional test data register that allows the manufacturer part number
and revision to be identified. The 32-bit identification register is partitioned into four fields:
Device version identifier 1st field
Device part number
Manufacturer’s JEDEC number
LSB
The first four bits beginning from MSB
2nd field
16 bits
3rd field
11 bits
4th field
1 bit — tied in High