
Samsung ASIC
3-37
STD130
ND5/ND5D2/ND5D4
5-Input NAND with 1X/2X/4X Drive
Logic Symbol
Cell Data
Switching Characteristics
ND5
(Typical process, 25
°
C, 1.8V, t
R
/t
F
= 0.15ns, SL: Standard Load)
Input Load (SL)
ND5D2
B
0.8
Gate Count
ND5D2
ND5
C
0.8
ND5D4
C
0.8
A
B
D
0.5
E
A
C
0.8
D
0.6
E
A
B
D
0.6
E
0.7
0.8
0.6
0.8
0.6
0.8
0.8
0.6
ND5
3.33
ND5D4
4.33
3.67
B
C
D
E
Y
A
Path
Parameter
Delay [ns]
SL = 2
0.078
0.081
0.179
0.184
0.078
0.081
0.193
0.185
0.078
0.080
0.206
0.185
0.080
0.081
0.195
0.201
0.080
0.081
0.208
0.197
<
Delay Equations [ns]
Group1*
0.037 + 0.020*SL
0.047 + 0.017*SL
0.159 + 0.010*SL
0.159 + 0.012*SL
0.038 + 0.020*SL
0.047 + 0.017*SL
0.173 + 0.010*SL
0.160 + 0.012*SL
0.038 + 0.020*SL
0.045 + 0.017*SL
0.185 + 0.010*SL
0.160 + 0.012*SL
0.040 + 0.020*SL
0.047 + 0.017*SL
0.175 + 0.010*SL
0.176 + 0.012*SL
0.040 + 0.020*SL
0.046 + 0.017*SL
0.187 + 0.010*SL
0.172 + 0.012*SL
Group2*
0.034 + 0.021*SL
0.047 + 0.017*SL
0.160 + 0.010*SL
0.167 + 0.010*SL
0.034 + 0.021*SL
0.046 + 0.017*SL
0.175 + 0.010*SL
0.168 + 0.010*SL
0.035 + 0.021*SL
0.046 + 0.017*SL
0.187 + 0.010*SL
0.168 + 0.010*SL
0.037 + 0.021*SL
0.046 + 0.017*SL
0.177 + 0.010*SL
0.184 + 0.010*SL
0.037 + 0.021*SL
0.046 + 0.017*SL
0.190 + 0.010*SL
0.180 + 0.010*SL
Group3*
0.030 + 0.021*SL
0.042 + 0.017*SL
0.161 + 0.010*SL
0.174 + 0.010*SL
0.030 + 0.021*SL
0.044 + 0.017*SL
0.175 + 0.010*SL
0.175 + 0.010*SL
0.031 + 0.021*SL
0.043 + 0.017*SL
0.188 + 0.010*SL
0.175 + 0.010*SL
0.032 + 0.021*SL
0.043 + 0.017*SL
0.178 + 0.010*SL
0.191 + 0.010*SL
0.032 + 0.021*SL
0.044 + 0.017*SL
0.190 + 0.010*SL
0.186 + 0.010*SL
A to Y
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
B to Y
C to Y
D to Y
E to Y
*Group1 : SL < 4, *Group2 : =
Truth Table
A
0
x
x
x
x
1
B
x
0
x
x
x
1
C
x
x
0
x
x
1
D
x
x
x
0
x
1
E
x
x
x
x
0
1
Y
1
1
1
1
1
0