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STD110
5-18
SEC ASIC
SPSRAMBW_HD
High Density Single-Port Synchronous SRAM with Bit-write
Parameter Description
SPSRAMBW_HD is the compiler that automatically generates symbol, netlist, timing model, power model
and layout according to the following parameters; Number of words(w), Number of bits per word(b), Column
mux(y) and number of banks(ba)
Parameters
YMUX = 4
Words (w)
ba = 1
Min
32
Max
1024
Step
16
ba = 2
Min
64
Max
2048
Step
32
Bpw (b)
Min
2
Max
128
Step
1
Pin Descriptions
YMUX = 8
64
2048
32
128
4096
64
2
64
1
YMUX = 16
128
4096
64
256
8192
128
2
32
1
YMUX = 32
256
8192
128
512
16384
256
2
16
1
Name
CK
I/O
Description
Clock
Clock input. CSN, WEN, A[] and DI[] are latched into the RAM on the rising edge
of CK. If CSN and WEN are low on the rising edge of CK, the RAM is in write
mode. If CSN is low and WEN is high on the rising edge of CK, the RAM is in
read mode.
Chip Enable input. The chip enable is active-low and is latched into the RAM on
the rising edge of CK. When CSN is low, the RAM is enabled for reading or writ-
ing, depending on the state of WEN. When CSN is high, the RAM goes to the
standby mode and is disabled for reading or writing. DOUT remains previous
data output.
Read or write enable input. The read/write enable is latched into the RAM on the
rising edge of CK. When WEN is low, data are written to the addressed location
and DOUT remains stable. When WEN is high, data from the addressed word
are presented at DOUT.
Bit-write enable input bus. The bit-write enable is latched into the RAM on the
rising edge of CK. Each bit of BWEN[] enables/disables the write operation of
corresponding data bit. BWEN[i] corresponds to DI[i] in bit-write. If WEN and
BWEN[0] are low and BWEN[1] is high, DI[0] is written into the memory location
specified on A[], but DI[1] is not written.
Data output enable input. The data output enable is asynchronously operated
regardless of the state of other inputs. When OEN is high, DOUT is disabled and
goes to high-impedance state.
Address input bus. The address is latched into the RAM on the rising edge of
CK.
Data input bus. Data are latched on the rising edge of CK. Data input is written
into the addressed location in write mode.
Data output bus. Data output is valid after the rising edge of CK while the RAM is
in read mode. Data output remains previous data output while the RAM is in
write mode.
CSN
Chip Enable
WEN
Read/Write
Enable
BWEN[]
Bit-Write
Enable
OEN
Data Output
Enable
A[]
Address
DI[]
Data Input
DOUT[]
Data Output