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1.12 Crystal Oscillator Consideration
Introduction
STD110
1-48
SEC ASIC
1.12.2.6 Pin Capacitance Rf / Rx Selection
Internal pin-to-ground and pin-to-pin capacitances, and PADA and PADY have
some effect on the oscillator. These capacitances are normally taken to be in the
range of 5 to 10pF, but they are extremely difficult to evaluate. Any measurement
of one such capacitance necessarily include effects from the others.
One advantage of the positive reactance oscillator is that the pin-to ground cap.
is paralleled by an external bulk capacitance, so a precise determination of their
value is unnecessary.
We would suggest that there is little justification for more precision than to assign
them a value of 7pF (PADA-to-ground and PADA-to-PADY). This value is
probably not in error by more than 3 or 4pF.
The PADY-to-ground cap. is not entirely a “pin capacitance”, but more like an
“equivalent output capacitance” of some 25 to 30pF, having to include the effect
of internal phase delays. This value varies to some extent with temperature,
process, and frequency.
1.12.2.7 Placement of Components
Noise glitches arising at PADA or PADY pins at the wrong time can cause a
miscount in the internal clock-generating circuitry. These kinds of glitches can be
produced through capacitive coupling between the oscillator components and
PCB traces carrying digital signals with fast rise and fall times.
For this reason, the oscillator components should be mounted close to the chip
and have short, direct traces to the PADA, PADY, and V
SS
pins.
If possible, use dedicated V
SS
and V
DD
pin for only crystal feedback amplifier.
1.12.3 TROUBLESHOOTING OSCILLATOR PROBLEMS
The first thing to consider in case of difficulty is that there may be significant
differences in stray caps between the test jig and the actual application,
particularly if the actual application is on a multi-layer board.
Noise glitches, that are not present in the test jig but are in the application board,
are another possibility. Capacitive coupling between the oscillator circuitry and
other signal has already been mentioned as a source of miscounts in the internal
clocking circuitry. Inductive coupling is also doubtful, if there is strong current
nearby. These problems are a function of the PCB layout.
Surrounding oscillator components with “quit” traces (for example, VCC and
ground) will alleviate capacitive coupling to signals having fast transition time. To
minimize inductive coupling, the PCB layout should minimize the areas of the
loops formed by oscillator components.
The loops demanding to be checked are as follows:
PADA through the resonator to PADY;
PADA through C1 to the V
SS
pin;
PADY through C2 to the V
SS
pin.
It is not unusual to find that the ground ends of C1 and C2 eventually connect up
to the V
SS
pin only after looping around the farthest ends of the board. Not good.
Finally, it should not be overlooked that software problems sometimes imitate the
symptoms of a slow-starting oscillator or incorrect frequency. Never
underestimate the perversity of a software problem.