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1.3 EDA Support
Introduction
STD110
1-4
SEC ASIC
1.3
EDA Support
SEC ASIC provides an efficient solution for multi-million gate ASICs in very deep
submicron (VDSM) technology. For large system-on-chip (SOC) type designs,
static verification methodology (static timing analysis and formal verification) will
shorten your design cycle time, which in turn will lessen today's ever-increasing
time-to-market pressure. Our Design-for-Test (DFT) methodology and service
take you through all phases of test insertion, test pattern generation and fault
grading to get high test coverage.
STD110 supports a rich collection of industry-standard EDA tools from Cadence,
Synopsys, Mentor graphics, and Avant! on multiple design platforms such as
Solaris and HP. Customers are allowed to choose among the industry-leading
EDA tools from design capture, synthesis, simulation, and DFT to layout. Several
powerful proprietary software tools are seamlessly integrated in our design kits to
improve your product quality.
For high simulation accuracy, STD110 uses a proprietary delay calculator. Cell
delay is calculated based on a matrix of delay parameters for each macrocell, and
signal interconnect delay is calculated based on the RC tree analysis.
1.4
Product Family
STD110 library include the following design elements:
I
Analog core cells
I
Digital core cells
I
Internal macrocells
I
Compiled macrocells
I
Input/Output cells.
1.4.1 ANALOG CORE CELLS
Introduction to Analog Cores
SEC ASIC is one of the leading suppliers of cell based mixed analog and digital
designs.Asaleadingsupplierofmixedanaloganddigitaldesigns,SECASIChas
more analog design experience than any other vendors. Analog has been and will
continue to be a part of the strategic focus at SEC ASIC. Analog design is a part
of the total SEC ASIC integrated design system. Workstation symbols are
supplied for analog cells and are entered as part of the design by the customer or
design center. SEC ASIC uses basically the same automatic layout and
verification tools for analog cells as for digital cells. Analog designs are processed
on the same production line as digital designs.
SEC's analog core family comprises ADC,DAC,PLL and sigma-delta ADC/DAC,
and their brief functional descriptions are introduced below.
[data sheets for all analog cores available]
Analog-to-Digital Converters
Analog-to-digital converters provide the link between the analog world and digital
systems. Due to their extensive use of analog and mixed analog-digital
operations, A/D converters often appear as the bottleneck in data processing
applications, limiting the overall speed or precision.
An A/D converter produces a digital output, D, as a function of the analog input, A:
D = f(A)
While the input can assume an infinite number of values, the output can be
selected from only a finite set of codes given by the converter's output word
length(i.e, resolution). Thus, the ADC must approximate each input level with one
of these codes, this process is so called 'quantization'.