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| 型號(hào)： | ST90158M7T6 |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁(yè)數(shù)： | 64/199頁(yè) |
| 文件大小： | 2813K |
| 代理商： | ST90158M7T6 |
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ST90158 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
DMA TRANSACTIONS
(Cont’d)
When selecting the DMA transaction with memory,
bit DCPR.RM (bit 0 of DCPR) must be cleared.
To select between using the ISR or the DMASR reg-
ister to extend the address, (see Memory Manage-
ment Unit chapter), the control bit DAPR.PS (bit 0
of DAPR) must be cleared or set respectively.
The DMA transaction Counter must be initialized
with the number of transactions to perform and will
be decremented after each transaction. The DMA
Address must be initialized with the starting ad-
dress of the DMA table and is increased after each
transaction. These two registers must be located
between addresses 00h and DFh of the Register
File.
Once a DMA channel is initialized, a transfer can
start. The direction of the transfer is automatically
defined by the type of peripheral and programming
mode.
Once the DMA table is completed (the transaction
counter reaches 0 value), an Interrupt request to
the CPU is generated.
When the Interrupt Pending (IP) bit is set by a
hardware event (or by software), and the DMA
Mask bit (DM) is set, a DMA request is generated.
If the Priority Level of the DMA source is higher
than, or equal to, the Current Priority Level (CPL),
the DMA transfer is executed at the end of the cur-
rent instruction. DMA transfers read/write data
from/to the location pointed to by the DMA Ad-
dress Register, the DMA Address register is incre-
mented and the Transaction Counter Register is
decremented. When the contents of the Transac-
tion Counter are decremented to zero, the DMA
Mask bit (DM) is cleared and an interrupt request
is generated, according to the Interrupt Mask bit
(End of Block interrupt). This End-of-Block inter-
rupt request is taken into account, depending on
the PRL value.
WARNING
. DMA requests are not acknowledged
if the top level interrupt service is in progress.
Figure 30. DMA Between Memory and Peripheral
n
IDCR
IVR
DAPR
DCPR
DATA
PAGED
REGISTERS
REGISTERS
SYSTEM
DMA
TRANSACTION
COUNTER
DMA
ADDRESS
FFh
F0h
EFh
E0h
DFh
MEMORY
0000h
DATA
ALREADY
TRANSFERRED
END OF BLOCK
INTERRUPT
SERVICE ROUTINE
DMA
TABLE
DMA TRANSACTION
ISR ADDRESS
0100h
VECTOR
TABLE
REGISTER FILE
PERIPHERAL
PAGED REGISTERS
9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST90158M9 | 8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM. OTP OR EPROM. 512 TO 2K RAM - ST9 + FAMILY |
| ST90158M9LVT6 | 8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM. OTP OR EPROM. 512 TO 2K RAM - ST9 + FAMILY |
| ST90158M9T6 | 8-BIT MICROCONTROLLER |
| ST90R158M9LVT6 | FUSE,5A,250V,5X20MM,FAST ACTING |
| ST90R158T6 | 8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM. OTP OR EPROM. 512 TO 2K RAM - ST9 + FAMILY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST90158M9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM. OTP OR EPROM. 512 TO 2K RAM - ST9 + FAMILY |
| ST90158M9LVT6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM. OTP OR EPROM. 512 TO 2K RAM - ST9 + FAMILY |
| ST90158M9Q6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM |
| ST90158M9T1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM |
| ST90158M9T6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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