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參數(shù)資料
| 型號： | ST72171 |
| 英文描述： | 8-BIT MCU WITH 8K FLASH. ADC. WDG. SPI. SCI. TIMERS SPGAS (SOFTWARE PROGRAMMABLE GAIN AMPLIFIERS). OP-AMP |
| 中文描述： | 8位8K閃存微控制器。 ADC的。水分散粒劑。的SPI。脊髓損傷。定時器SPGAS（軟件可編程增益放大器）。運放 |
| 文件頁數(shù)： | 22/93頁 |
| 文件大?。?/td> | 915K |
| 代理商： | ST72171 |
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ST72E121 ST72T121
POWER SAVING MODES
(Cont’d)
4.4.4 Halt Mode
The Halt mode is the MCU lowest power con-
sumption mode. The Halt mode is entered by exe-
cuting the HALT instruction. The internal oscillator
is then turned off, causing all internal processing to
be stopped, including the operation of the on-chip
peripherals. The Halt mode cannot be used when
the watchdog is enabled, if the HALT instruction is
executed while the watchdog system is enabled, a
watchdog reset is generated thus resetting the en-
tire MCU.
When entering Halt mode, the I bit in the CC Reg-
ister is cleared so as to enable External Interrupts.
If an interrupt occurs, the CPU becomes active.
The MCU can exit the Halt mode upon reception of
an interrupt or a reset. Refer to the Interrupt Map-
ping Table. The oscillator is then turned on and a
stabilization time is provided before releasing CPU
operation. The stabilization time is 4096 CPU clock
cycles.
After the start up delay, the CPU continues oper-
ation by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
Figure 17. HALT Flow Chart
N
N
EXTERNAL
INTERRUPT
1)
RESET
HALT INSTRUCTION
4096 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU CLOCK
I-BIT
OSCILLATOR
PERIPH. CLOCK
2)
ON
OFF
ON
SET
CPU CLOCK
I-BIT
OSCILLATOR
PERIPH. CLOCK
OFF
OFF
OFF
CLEARED
Y
Y
WDG
ENABLED
N
Y
RESET
WATCHDOG
1) or some specific interrupts
2) if reset PERIPH. CLOCK = ON ; if interrupt
PERIPH. CLOCK = OFF
Note:
Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
CPU CLOCK
I-BIT
OSCILLATOR
PERIPH. CLOCK
ON
ON
ON
SET
22
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