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| 型號： | ST72171 |
| 英文描述： | 8-BIT MCU WITH 8K FLASH. ADC. WDG. SPI. SCI. TIMERS SPGAS (SOFTWARE PROGRAMMABLE GAIN AMPLIFIERS). OP-AMP |
| 中文描述： | 8位8K閃存微控制器。 ADC的。水分散粒劑。的SPI。脊髓損傷。定時器SPGAS（軟件可編程增益放大器）。運放 |
| 文件頁數(shù)： | 21/93頁 |
| 文件大小： | 915K |
| 代理商： | ST72171 |
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ST72E121 ST72T121
4.4 POWER SAVING MODES
4.4.1 Introduction
There are three Power Saving modes. Slow Mode
is selected by setting the relevant bits in the Mis-
cellaneous register. Wait and Halt modes may be
entered using the WFI and HALT instructions.
4.4.2 Slow Mode
In Slow mode, the oscillator frequency can be di-
vided by a value defined in the Miscellaneous
Register. The CPU and peripherals are clocked at
this lower frequency. Slow mode is used to reduce
power consumption, and enables the user to adapt
clock frequency to available supply voltage.
4.4.3 Wait Mode
Wait mode places the MCU in a low power con-
sumption mode by stopping the CPU. All peripher-
als remain active. During Wait mode, the I bit (CC
Register) is cleared, so as to enable all interrupts.
All other registers and memory remain unchanged.
The MCU will remain in Wait mode until an Inter-
rupt or Reset occurs, whereupon the Program
Counter branches to the starting address of the In-
terrupt or Reset Service Routine.
The MCU will remain in Wait mode until a Reset or
an Interrupt occurs, causing it to wake up.
Refer to
Figure 16
below.
Figure 16. WAIT Flow Chart
WFI INSTRUCTION
RESET
INTERRUPT
Y
N
N
Y
CPU CLOCK
I-BIT
OSCILLATOR
PERIPH. CLOCK
ON
ON
OFF
CLEARED
Note:
Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
4096 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU CLOCK
I-BIT
OSCILLATOR
PERIPH. CLOCK
ON
ON
ON
SET
CPU CLOCK
I-BIT
OSCILLATOR
PERIPH. CLOCK
ON
ON
ON
SET
21
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