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參數(shù)資料
| 型號： | ST72171 |
| 英文描述： | 8-BIT MCU WITH 8K FLASH. ADC. WDG. SPI. SCI. TIMERS SPGAS (SOFTWARE PROGRAMMABLE GAIN AMPLIFIERS). OP-AMP |
| 中文描述： | 8位8K閃存微控制器。 ADC的。水分散粒劑。的SPI。脊髓損傷。定時器SPGAS（軟件可編程增益放大器）。運放 |
| 文件頁數(shù)： | 17/93頁 |
| 文件大?。?/td> | 915K |
| 代理商： | ST72171 |
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ST72E121 ST72T121
RESET
(Cont’d)
3.2.4 Low Voltage Detector Reset
The on-chip Low Voltage Detector (LVD) gener-
ates a static reset when the supply voltage is be-
low a reference value. The LVD functions both
during power-on as well as when the power supply
drops (brown-out). The reference value for a volt-
age drop is lower than the reference value for pow-
er-on in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup-
ply (hysteresis).
The LVD Reset circuitry generates a reset when
V
DD
is below:
V
LVDUP
when V
DD
is rising
V
LVDDOWN
when V
DD
is falling
Provided the minimun V
DD
value (guaranteed for
the oscillator frequency) is above V
LVDDOWN
, the
MCU can only be in two modes:
- under full software control or
- in static safe reset
In this condition, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
In noisy environments, the power supply may drop
for short periods and cause the Low Voltage De-
tector to generate a Reset too frequently. In such
cases, it is recommended to use devices without
the LVD Reset option and to rely on the watchdog
function to detect application runaway conditions.
Figure 12. Low Voltage Detector Reset Function
Figure 13. Low Voltage Detector Reset Signal
Note:
See electrical characteristics for values of
V
LVDUP
and V
LVDDOWN
Figure 14. Temporization timing diagram after an internal Reset
LOW VOLTAGE
DETECTOR RESET
V
DD
FROM
WATCHDOG
RESET
RESET
RESET
V
DD
V
LVDUP
V
LVDDOWN
V
DD
Addresses
$FFFE
Temporization (4096 CPU clock cycles)
V
LVDUP
17
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