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參數(shù)資料
| 型號： | ST72121J4 |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| 中文描述： | 8位微控制器與2/4/8K字節(jié)在系統(tǒng)可編程閃存 |
| 文件頁數(shù)： | 30/93頁 |
| 文件大?。?/td> | 915K |
| 代理商： | ST72121J4 |
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ST72E121 ST72T121
5.2 WATCHDOG TIMER (WDG)
5.2.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
5.2.2 Main Features
I
Programmable timer (64 increments of 12288
CPU cycles)
I
Programmable reset
I
Reset (if watchdog activated) after a HALT
instruction or when the T6 bit reaches zero
I
Hardware Watchdog selectable by option byte
I
Watchdog Reset indicated by status flag (in
versions with Safe Reset option only)
5.2.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 12,288 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
Figure 20. Watchdog Block Diagram
RESET
WDGA
7-BIT DOWNCOUNTER
f
CPU
T6
T0
CLOCK DIVIDER
÷
12288
WATCHDOG CONTROL REGISTER (CR)
T1
T2
T3
T4
T5
30
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