參數(shù)資料
型號(hào): ST72121J2
元件分類: 8位微控制器
英文描述: 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
中文描述: 8位微控制器與2/4/8K字節(jié)在系統(tǒng)可編程閃存
文件頁數(shù): 23/93頁
文件大?。?/td> 915K
代理商: ST72121J2
23/93
ST72E121 ST72T121
4.5 MISCELLANEOUS REGISTER
The Miscellaneous register allows to select the
SLOW operating mode, the polarity of external in-
terrupt requests and to output the internal clock.
Register Address: 0020h
Reset Value: 0000 0000 (00h)
Read/Write
Bit 7:6 =
PEI[3:2]
External Interrupt EI3 and EI2
Polarity Options
.
These bits are set and cleared by software. They
determine which event on EI2 and EI3 causes the
external interrupt according to
Table 6
.
Table 6. EI2 and EI3 External Interrupt Polarity
Options
Note:
Any modification of one of these two bits re-
sets the interrupt request related to this interrupt
vector.
Bit 5 =
MCO
Main Clock Out
This bit is set and cleared by software. When set, it
enables the output of the Internal Clock on the
PPF0 I/O port.
0 - PF0 is a general purpose I/O port.
1 - MCO alternate function (f
CPU
is output on PF0
pin).
Bit 4:3 =
PEI[1:0]
External Interrupt EI1 and EI0
Polarity Options
.
These bits are set and cleared by software. They
determine which event on EI0 and EI1 causes the
external interrupt according to
Table 7
.
Table 7. EI0 and EI1 External Interrupt Polarity
Options
Note:
Any modification of one of these two bits re-
sets the interrupt request related to this interrupt
vector.l
Bit 2:1 =
PSM[1:0]
Prescaler for Slow Mode.
These bits are set and cleared by software. They
determine the CPU clock when the SMS bit is set
according to the following table.
Table 8. f
CPU
Value in Slow Mode
Bit 0 =
SMS
Slow Mode Select
This bit is set and cleared by software.
0: Normal Mode - f
CPU
= f
OSC
/ 2
(Reset state)
1: Slow Mode - the f
CPU
value is determined by the
PSM[1:0] bits.
7
0
PEI3 PEI2 MCO PEI1 PEI0
PSM1
PSM0
SMS
MODE
PEI3
PEI2
Falling edge and low level
(Reset state)
Falling edge only
Rising edge only
Rising and falling edge
0
0
1
0
1
0
1
1
MODE
PEI1
PEI0
Falling edge and low level
(Reset state)
Falling edge only
Rising edge only
Rising and falling edge
0
0
1
0
1
0
1
1
f
CPU
Value
f
OSC
/ 4
f
OSC
/ 16
f
OSC
/ 8
f
OSC
/ 32
PSM1
0
0
1
1
PSM0
0
1
0
1
23
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