- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372305 > ST62T94M8 Telecommunication IC PDF資料下載
參數(shù)資料
| 型號(hào)： | ST62T94M8 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 50/82頁 |
| 文件大?。?/td> | 870K |
| 代理商： | ST62T94M8 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當(dāng)前第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
50/82
ST62T18C/E18C
AUTO-RELOAD TIMER
(Cont’d)
AR Status Control Register 1(ARSC1)
Address: E7h
—
Read/Write
Bist 7-5 =
PS2-PS0
:
Prescaler Division Selection
Bits 2-0.
These bits determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by
these bits. The prescaler division ratio is listed in the
following table:
Table 16. Prescaler Division Ratio Selection
Bit 4 =
D4
:
Reserved
. Must be kept reset.
Bit 3-2 =
SL1-SL0
:
Timer Input Edge Control Bits 1-
0.
These bits control the edge function of the Timer
input pin for external synchronization. If bit SL0 is re-
set, edge detection is disabled; if set edge detection
is enabled. If bit SL1 is reset, the AR Timer input pin
is rising edge sensitive; if set, it is falling edge sen-
sitive.
Bit 1-0 =
CC1-CC0
:
Clock Source Select Bit 1-0.
These bits select the clock source for the AR Timer
through the AR Multiplexer. The programming of
the clock sources is explained in the following
Table
3
:
Table 17. Clock Source Selection.
AR Load Register ARLR
. The ARLR load register
is used to read or write the ARTC counter register
“on the fly” (while it is counting). The ARLR regis-
ter is not affected by system reset.
AR Load Register (ARLR)
Address: EBh
—
Read/Write
Bit 7-0 =
D7-D0
:
Load Register Data Bits.
These
are the load register data bits.
AR Reload/Capture Register
. The ARRC reload/
capture register is used to hold the auto-reload
value which is automatically loaded into the coun-
ter when overflow occurs.
AR Reload/Capture (ARRC)
Address: E9h
—
Read/Write
Bit 7-0 =
D7-D0
:
Reload/Capture Data Bits
. These
are the Reload/Capture register data bits.
AR Compare Register
. The CP compare register
is used to hold the compare value for the compare
function.
AR Compare Register (ARCP)
Address: EAh
—
Read/Write
Bit 7-0 =
D7-D0
:
Compare Data Bits
. These are
the Compare register data bits.
7
0
PS2
PS1
PS0
D4
SL1
SL0
CC1
CC0
PS2
0
0
0
0
1
1
1
1
PS1
0
0
1
1
0
0
1
1
PS0
0
1
0
1
0
1
0
1
ARPSC Division Ratio
1
2
4
8
16
32
64
128
SL1
X
0
1
SL0
0
1
1
Edge Detection
Disabled
Rising Edge
Falling Edge
CC1
0
0
1
1
CC0
0
1
0
1
Clock Source
F
int
F
int
Divided by 3
ARTIMin Input Clock
Reserved
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
50
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST6228C | 8-BIT MICROCONTROLLER ( MCU ) WITH OTP. ROM. FASTR A/D CONVERTER. 8-BIT AUTO-RELOAD TIMER. UART. OSG. SAFE RESET AND 28 PINS |
| ST62E28CF1 | 8-BIT MICROCONTROLLER ( MCU ) WITH OTP. ROM. FASTR A/D CONVERTER. 8-BIT AUTO-RELOAD TIMER. UART. OSG. SAFE RESET AND 28 PINS |
| ST62P28CB1 | 8-BIT MICROCONTROLLER ( MCU ) WITH OTP. ROM. FASTR A/D CONVERTER. 8-BIT AUTO-RELOAD TIMER. UART. OSG. SAFE RESET AND 28 PINS |
| ST62P28CB3 | 8-BIT MICROCONTROLLER ( MCU ) WITH OTP. ROM. FASTR A/D CONVERTER. 8-BIT AUTO-RELOAD TIMER. UART. OSG. SAFE RESET AND 28 PINS |
| ST62P28CB6 | 8-BIT MICROCONTROLLER ( MCU ) WITH OTP. ROM. FASTR A/D CONVERTER. 8-BIT AUTO-RELOAD TIMER. UART. OSG. SAFE RESET AND 28 PINS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST63/69/23 | 制造商:Block 功能描述:Control panel transformer, 63VA, 230V |
| ST6-30 | 制造商:SUPERWORLD 制造商全稱:Superworld Electronics 功能描述:POWER TRANSFORMER |
| ST630/69/23 | 制造商:Block USA Inc. 功能描述:Control panel transformer, 630VA, 230V |
| ST6306 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| ST6307 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。