參數(shù)資料
型號(hào)： ST52F514Y1M6
英文描述： IC MAX 7000 CPLD 256 256-FBGA
中文描述： 微控制器
文件頁(yè)數(shù)： 98/106頁(yè)
文件大?。?/td> 648K
代理商： ST52F514Y1M6
ST52F510/F513/F514
98/106
is taking place with an external device. When this
occurs, the transfer continues uninterrupted; and
the softwarewriting will be unsuccessful.
Write collisions can occur both in master and slave
mode.
Note:
a “read collision” will never occur since the
data byte received is placed in a buffer, in which
access is always synchronous with the ICU
operation.
In Slave mode
When the CPHA bit is set:
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
SPI_OUT register and output the MSBit on to the
external MISO pin of the slave device.
The SS pin low state enables the slave device, but
the outputof theMSBit onto the MISO pin does not
take place until the first data transfer clock edge
occurs.
When the CPHA bit is reset:
Data is latched on the occurrence of the first clock
transition. The slave device doesn’t have a way of
knowing when that transition will occur; therefore,
the slave device collision occurs when software
attempts to write the SPI_OUT register after its SS
pin has been pulled low.
For this reason, the SS pin must be high, between
each data byte transfer, in order to allow the CPU
to write inthe SPI_OUT register withoutgenerating
a write collision.
In Master mode
Collision in the master device is defined as a write
of the SPI_OUT register, while the internal serial
clock (SCK) is in the process of transfer.
The SS pin signal must always be high on the
master device.
Figure 15.3 CHPA/SS TimingDiagram
WCOL bit
The WCOL bit in the SPI_STATUS_CR register is
set if a write collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
The WCOL bit is cleared by a software sequence
(see Section 15.5).
15.4.5 Master Mode Fault.
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
Master mode fault affects the SPI peripheral in the
following ways:
– The MODF bit is set and an SPI interrupt is
generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output from
the device and disables the SPI peripheral.
– The MSTR bit is reset, forcing the device into
slave mode.
Clearing the MODF bit is done through a software
sequence:
1. Aread or write access to the SPI_STATUS_CR
register while the MODF bit is set.
2. A write to the SPI_CR register.
Note:
To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing
sequence of the MODF bit. The SPE and MSTR
bits maybe restored to their orignal state during or
after this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits, while the MODF bit is set (except
in the MODF bit clearing sequence).
In a slave device the MODF bit can’t be set, but in
a multi master configuration the device can be in
slave mode with this MODF bit set.
The MODFbit indicatesthat there might have been
a multi-master conflict for system control and
allows a proper exit from system operation to a
reset or default system state using an interrupt
routine.
MOSI/MISO
Master SS
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
Byte 1
Byte 2
Byte 3
相關(guān)PDF資料
PDF描述
ST52F514Y3B6 IC MAX 7000 CPLD 128 144-TQFP
ST52F514Y3M6 IC MAX 7000 CPLD 256 144-TQFP
ST5R33 Programmable Logic IC; Logic Type:Programmable; No. of Macrocells:102; Package/Case:144-TQFP; Leaded Process Compatible:No; Number of Circuits:1728; Peak Reflow Compatible (260 C):No; Mounting Type:surface mount RoHS Compliant: No
ST5R50 ; No. of Macrocells:64; IC Generic Number:; No. of Outputs:68; Number of Inputs:68; Operating Temp. Max:70 C; Operating Temp. Min:0 C; Propagation Delay:10ns; No. of Pins:44
ST5R25 Programmable Logic IC; Logic Type:Programmable; No. of Macrocells:32; Package/Case:44-PLCC; Mounting Type:Surface Mount
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST52F514Y3B6 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Microcontroller
ST52F514Y3M6 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Microcontroller
ST52F514YMM6 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI
ST-52K 制造商:Eaton Heinemann 功能描述:ST52K
ST52N 制造商:Eaton Corporation 功能描述:
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