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參數資料
| 型號： | ST52F514Y1M6 |
| 英文描述： | IC MAX 7000 CPLD 256 256-FBGA |
| 中文描述： | 微控制器 |
| 文件頁數： | 96/106頁 |
| 文件大小： | 648K |
| 代理商： | ST52F514Y1M6 |
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ST52F510/F513/F514
96/106
Figure 15.2 Serial Peripheral Interface Block Diagram
Procedure
– Select theSPR0, SPR1and SPR2 bits to define
the serial clock baud rate (seeSPI_CR register).
– Select the CPOL and CPHA bits to defineone of
the four relationships between the data transfer
and the serial clock (see Figure 15.4).
– The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence.
– The MSTR and SPE bits must be set (they re-
main set only if the SS pin is connectedto a high
level signal).
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Transmit sequence
Transmit sequence begins when a byte is written in
the SPI_OUT register.
The databyte is loaded in parallelinto the 8-bitshift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if the SPIE bit is set.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPI_IN register is
read, the SPI peripheral returns this buffered
value. Clearing the SPIF bit is performed by the
following software sequence:
1. An access to the SPI_STATUS_CR register
while the SPIF bit is set
2. A read to the SPI_IN register.
Note:
While the SPIF bit is set, all writes to the
SPI_OUT
register
are
SPI_STATUS_CR register is read.
inhibited
until
the
SPI_IN
Read Buffer
8-Bit Shift Register
Write
Read
Internal Bus
SPI
STATE
SPIE
SPE
MSTR
CPHA
SPR0
SPR1
CPOL
SPIF WCOL
MODF
SERIAL
CLOCK
GENERATOR
MOSI
MISO
SS
SCK
CONTROL
SPI_CR
SPI_STATUS_CR
-
IT
request
MASTER
CONTROL
SPR2
OR
SSI
SSM
SOD
SPI_OUT
相關PDF資料 |
PDF描述 |
|---|---|
| ST52F514Y3B6 | IC MAX 7000 CPLD 128 144-TQFP |
| ST52F514Y3M6 | IC MAX 7000 CPLD 256 144-TQFP |
| ST5R33 | Programmable Logic IC; Logic Type:Programmable; No. of Macrocells:102; Package/Case:144-TQFP; Leaded Process Compatible:No; Number of Circuits:1728; Peak Reflow Compatible (260 C):No; Mounting Type:surface mount RoHS Compliant: No |
| ST5R50 | ; No. of Macrocells:64; IC Generic Number:; No. of Outputs:68; Number of Inputs:68; Operating Temp. Max:70 C; Operating Temp. Min:0 C; Propagation Delay:10ns; No. of Pins:44 |
| ST5R25 | Programmable Logic IC; Logic Type:Programmable; No. of Macrocells:32; Package/Case:44-PLCC; Mounting Type:Surface Mount |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ST52F514Y3B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514Y3M6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514YMM6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI |
| ST-52K | 制造商:Eaton Heinemann 功能描述:ST52K |
| ST52N | 制造商:Eaton Corporation 功能描述: |
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