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參數(shù)資料
| 型號(hào)： | ST52F514Y1M6 |
| 英文描述： | IC MAX 7000 CPLD 256 256-FBGA |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 81/106頁 |
| 文件大?。?/td> | 648K |
| 代理商： | ST52F514Y1M6 |
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ST52F510/F513/F514
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13.2 SCI Transmitter Block
The SCI Transmitter Blockconsists of thefollowing
blocks:
SCDR_TX
and
synchronized, respectively, with the clock master
signal (CKM) and the CLOCK_TX.
The whole block receives the settings for the
following
transmission
Configuration Register:
I
8 bit length, 1 stop bit, no parity bit
SHIFT
REGISTER,
modes
through
the
I
8 bit length, 2 stop bit, no parity bit
I
8 bit length, 1 stop bit, with parity bit
I
9 bit length, 1 stop bit, no parity bit
In case of 9 bit frame transmission, the most
significative bit arrives through the bit PAR/T8 (bit
2) of the SCI_CR1 Configuration Register. In an 8-
bit transmission, instead, this bit is used to
configure the data format: in particular to choose
the polaritycontrol (even or odds)to implement the
parity check (see above).
After a RESET, the SCDR_TX block is in IDLE
state until it receives an enabling signal by writing
the TXSTRT bit of the SCI_CR2 Configuration
Register.
The data is loaded on the Peripheral Register
SCI_OUT
(address 23 017h)
instruction
LPPR,
LDPI
transmission is enabled, the data to be transmitted
is
transferred
from
the
SCDR_TX block and the TXEM flag (bit 1) of the
SCI Status Register is reset to 0 to indicate
SCDR_TX block is full.
If the core supplies new data, this could not be
loaded inthe SCDR_TX blockuntil thecurrent data
has not been unloaded on the Shift Register block.
Meaning that only when TXEM is 1 data can be
loaded in the SCDR_TX Block.
When the SHIFT REGISTER Block loads the data
to be transmitted on an internal buffer, the TXEND
flag (bit 0) of the SCI Status Register is reset to 0
to indicate the beginning of a new transmission. At
the end oftransmission TXEND isset to 1, allowing
new data coming from SCDR_TX to be loaded in
the SHIFT REGISTER.
It is important to underline that TXEND = 1 does
not mean SCDR_TX is ready to receive a new
data. Forthis reason,it is better to utilize the TXEM
signal to synchronize the load instruction to the
SCI TRANSMITTER block
If the TXSTRT bit is reset, the transmission is
stopped, but the SCI Transmitter block completes
the transmission in progress before resetting.
by using
LDPE.
the
the
or
If
Output
Register
to
13.3 Baud Rate Generator Block
The Baud Rate Generator Block performs the
division of the clockmaster signal (CKM) in a set of
synchronism
frequencies
reception/transmission on the external line.
Reception frequency (CLOCK_RX) is 16 times
higher
than
the
transmission
(CLOCK_TX).
To adapt the Baud Rate Generator to the clock
master frequency supplied by the user, a 12-bit
Prescaler must be programmed by loading the
Configuration Registers SCI_CR2 (PRESC_H bit
11:8 of the 12 bit prescaler) and SCI_CR3
(PRESC_L bit 7:0 of the 12 bit prescaler). The
prescaler allows the programming of all standard
Baud Rates by using the most common clock
master sources.
The Prescaler value can be obtained by the
following formula:
for
the
serial
bit
frequency
Where CKM is the clock master frequency
(expressed in Hz) and BAUD is the desired Baud
Rate (expressed in bit/second). The obtained
value is rounded to the nearest integer value. This
rounding can cause an error in the obtained Baud
Rate. This error must be lower than 3%. To verify
that the PRESC value satisfies this constrain, the
obtained Baud Rate must be computed by
inverting the previous formula:
then the following relation can be used to verify
that the difference with the desired Baud Rate is
lower than 3%:
Table 13.1 shows the recommended Prescaler
values for common clock master frequencies. To
get more precision in Baud Rate, standard quartz
frequencies for serial communication can be used.
The corresponding Prescaler values for these
frequencies are showed in the Table 13.2.
PRESC
round
BAUD
×
16
-----------------------------
=
BAUD
PRESC
×
16
-------------------------------
=
-------------------------------------------
–
BAUD
0.03
<
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST52F514Y3B6 | IC MAX 7000 CPLD 128 144-TQFP |
| ST52F514Y3M6 | IC MAX 7000 CPLD 256 144-TQFP |
| ST5R33 | Programmable Logic IC; Logic Type:Programmable; No. of Macrocells:102; Package/Case:144-TQFP; Leaded Process Compatible:No; Number of Circuits:1728; Peak Reflow Compatible (260 C):No; Mounting Type:surface mount RoHS Compliant: No |
| ST5R50 | ; No. of Macrocells:64; IC Generic Number:; No. of Outputs:68; Number of Inputs:68; Operating Temp. Max:70 C; Operating Temp. Min:0 C; Propagation Delay:10ns; No. of Pins:44 |
| ST5R25 | Programmable Logic IC; Logic Type:Programmable; No. of Macrocells:32; Package/Case:44-PLCC; Mounting Type:Surface Mount |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52F514Y3B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514Y3M6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514YMM6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI |
| ST-52K | 制造商:Eaton Heinemann 功能描述:ST52K |
| ST52N | 制造商:Eaton Corporation 功能描述: |
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