參數(shù)資料
型號: ST52F514Y0M6
英文描述: IC MAX 7000 CPLD 64 44-TQFP
中文描述: 微控制器
文件頁數(shù): 51/106頁
文件大小: 648K
代理商: ST52F514Y0M6
ST52F510/F513/F514
51/106
7.6.1 Configuration Registers.
Port A Pull-Up Register (PORT_A_PULLUP)
Configuration Register 24 (018h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-0:
PUA7-0
Port A pull-up (see Table 7.1)
0: Port A pin without pull-up
1: Port A pin with pull-up
Port A Option Register (PORT_A_OR)
Configuration Register 25 (019h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-0:
ORA7-0
Port A option (see Table 7.1)
Port A Data Direction Register (PORT_A_DDR)
Configuration Register 26 (01Ah) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-0:
DDRA7-0
Port A direction (see Table 7.1)
0: Port A pin configured as input
1: Port A pin configured as output
Port A Alternate Fuction (PORT_A_AF)
Configuration Register 27 (01Bh) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:
AFA7
Alternate Function PA7
0: Digital I/O
1: INT
Bit 6:
AFA6
Alternate Function PA6
0: Digital I/O
1: T0OUT
Bit 5:
AFA5
Alternate Function PA5
0: Digital I/O
1: TCLK
Bit 4:
AFA4
Alternate Function PA4
0: Digital I/O
1: TSTRT
Bit 3:
AFA3
Alternate Function PA3
0: Digital I/O
1: TRES
Bit 2:
AFA2
Alternate Function PA2
0: Digital I/O
1: T1OUT
Bit 1:
AFA1
Alternate Function PA1
0: Digital I/O
1: SDA
Bit 0:
AFA0
Alternate Function PA0
0: Digital I/O
1: SCL
7
0
PUA7
PUA6
PUA5
PUA4
PUA3
PUA2
PUA1
PUA0
7
0
ORA7
ORA6
ORA5
ORA4
ORA3
ORA2
ORA1
ORA0
7
0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
7
0
AFA7
AFA6
AFA5
AFA4
AFA3
AFA2
AFA1
AFA0
Table 7.1 Pin mode configuration
MODE
PU
OR
DDR
Input high impedance
0
0
0
Input with pull-up
1
0
0
Interrupt without pull-up
0
1
0
Interrupt with pull-up
1
1
0
Output push-pull
0
0
1
Output with pull-up
1
0
1
Output open drain
0
1
1
Output weak pull-up
1
1
1
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