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參數(shù)資料
| 型號(hào)： | ST52F514Y0M6 |
| 英文描述： | IC MAX 7000 CPLD 64 44-TQFP |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 20/106頁 |
| 文件大?。?/td> | 648K |
| 代理商： | ST52F514Y0M6 |
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ST52F510/F513/F514
20/106
3 ADDRESSING SPACES
ST52F510/F513/F514
addressing spaces:
I
Register File
I
Program/Data Memory
has
six
separate
I
Stacks
I
Input Registers
I
Output Registers
I
Configuration Registers
Each space is addressed by a load type instruction
that indicatesthe source and thedestination space
in the mnemonic code (see Figure 3.1).
3.1 Memory Interface
The read/write operation in the space addresses
are managed by the Memory Interface, which can
recognize the type of memory addressed and set
the appropriateaccess time and mode.
In addition, the Memory Interface manages the In
Application Programming (IAP) functions in Flash
devices like writing cycle and memory write
protection.
Figure 3.1 Addressing Spaces
3.2 Register File
The Register File consists of up to 256 general
purpose 8-bit RAM locations called “registers” in
order to recall the functionality.
The Register Fileexchanges datawith all theother
addressing spaces and is used by the ALU to
perform all the arithmetic and logic instructions.
These instructions have any Register File address
as operands.
Data canbemoved from one location to another by
using the LDRR instruction; see further ahead for
information on the instruction used to move data
between
the
Register
addressing spaces.
File
and
the
other
3.3 Program/Data Memory
The Program/Data Memory consists of both non-
volatile memory (Flash, EEPROM) and RAM
memory benches.
Non-volatile memory (NVM) is mainly used to store
the user program and can also be used to store
permanent data (constant, look-up tables).
Each RAM bench consists of 128/256 locations
used to store run-time user data. At least one
bench is presentin the devices. RAM benches are
also used to implement both System and User
Stacks.
CU
DPU
ALU
PERIPHERAL
BLOCK
REGISTER FILE
INPUT REGISTERS
NON VOLATILE MEMORY
RAM BANKS
AND STACKS
PROGRAM/DATA MEMORY
STFive CORE
ON CHIP PERIPHERALS
OUTPUT
REGISTERS
CONFIGURATION
REGISTERS
PERIPHERAL
BLOCK
PERIPHERAL
BLOCK
LDER
LDRE
LDRI
LDCE
LDCR
DECISION
PROCESSOR
REGISTERS
LDFR
LDPE
LDPR
LDCNF
PROGRAM
COUNTER
PGSETR
GETPG
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST52F514Y1B6 | MAX II CPLD 240 LE 100-TQFP |
| ST52F514Y1M6 | IC MAX 7000 CPLD 256 256-FBGA |
| ST52F514Y3B6 | IC MAX 7000 CPLD 128 144-TQFP |
| ST52F514Y3M6 | IC MAX 7000 CPLD 256 144-TQFP |
| ST5R33 | Programmable Logic IC; Logic Type:Programmable; No. of Macrocells:102; Package/Case:144-TQFP; Leaded Process Compatible:No; Number of Circuits:1728; Peak Reflow Compatible (260 C):No; Mounting Type:surface mount RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52F514Y1B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514Y1M6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514Y3B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514Y3M6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514YMM6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI |
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