參數(shù)資料
型號(hào): ST52F514G1M6
英文描述: IC MAX 7000 CPLD 64 44-PLCC
中文描述: 微控制器
文件頁(yè)數(shù): 48/106頁(yè)
文件大?。?/td> 648K
代理商: ST52F514G1M6
ST52F510/F513/F514
48/106
(*) Values by design (not characterized)
Internal Oscillator Calibration (OSC_SET)
Option Byte 2 (02h)
Reset Value: 0000 0000 (00h)
Bit 7-6: Not Used
Bit 5-0:
OSPAR5-0
Internal Oscillator Parameters
These bitsare used in order to calibrate the
precision of the internal oscillator working
at 10 MHz. The six bits enable some
current generators with steps of 5
μ
A
corresponding to interval of frequency of
100KHz
.
Warning:
allowed is101000 (40). The value coresponding to
the 10MHz by design is 010100 (20).
the
maximum
configuration
value
PLVD Control Register (PLVD_CR)
Option Byte 3 (03h)
Reset Value: 0000 0000 (00h)
Bit 7-2: Not Used
Bit 1-0:
PLVD1-0
PLVD detection levels
00: PLVD disabled
01: Lowest detection level
10: Medium detection level
11: Highest detection level
Wake-Up Time Prescaler (WAKEUP)
Option Byte 7 (07h)
Reset Value: 0000 0000 (00h)
Bit 7-0:
WK7-0
Wake-up prescaler
This byte determinates the time delay for
the stabilization of the oscillator after an
External Reset or a POR and after the
wake-up from Halt. The time delay is
computed
according
formula:
to
the
following
Warning:
the value 255 for WAKEUP is not
allowed. If the internal clock is used as clock
source the prescaler is not used.
Table 6.2 Recomended Gains for the most common frequencies
Frequency
Recommend
Gain Stages
CKPAR2-0
Oscillation
Start Times*
Settling Times for
40%-60% duty-cycle*
External Clock
0
000
-
-
5 MHz
1
001
100
μ
s
110
μ
s
10 MHz
3
011
80
μ
s
85
μ
s
20 MHz
6
111
133
μ
s
143
μ
s
7
0
-
-
OSPAR5 OSPAR4 OSPAR3 OSPAR2 OSPAR1 OSPAR0
7
0
-
-
-
-
-
-
PLVD1
PLVD0
7
0
WK7
WK6
WK5
WK4
WK3
WK2
WK1
WK0
Delay
4096
WAKEUP
1
+
(
)
Tclk
×
×
=
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