參數(shù)資料
型號(hào): ST52F514F3M6
英文描述: IC MAX 7000 CPLD 256 256-FBGA
中文描述: 微控制器
文件頁數(shù): 64/106頁
文件大?。?/td> 648K
代理商: ST52F514F3M6
ST52F510/F513/F514
64/106
10 10-BIT A/D CONVERTER
10.1 Introduction
ST52F510/F513/F514 A/D Converter is a 10-bit
analog to digital converter with up to 8 analog
inputs.
The
A/D
converter
conversion timeof 10
μ
s in fastmode and of 20
μ
s
in slow mode. Thisperiod also includes the time of
the integral Sample and Hold circuitry, which
minimizes the need for external components and
allows quick sampling of the signal for the
minimum warping effect and integral conversion
error.
In addition the peripheral performs a calibration
procedure in order to get the maximum precision
allowed in the data of conversion. The calibration
procedure is performed in two phases: the pre-
charging phase and the tuning phase. The pre-
charging process can be executed, after the
peripheral start, to set-up the internal references
and to speed-up the tuning process. The tuning
process
is
carried-out
conversion.
offers
a
typical
during
the
channels
Note:
The user must be take in account both the
pre-charging timeand somedummy conversion(at
least 20) for the tuning before starting the data
acquisition. It is recommended to repeat this
procedure at the start-up and after a long time
peripheral stop.
Figure 10.1 A/D Converter Structure
The pre-charging process starts by starting the
peripheral by setting to 1 theSTR bit of the AD_CR
Configuration
Register.
calibration procedure, the pre-charging phase can
be skippedwhen not necessary (for example when
single conversions are performed). The user can
disable the pre-charging by setting the PRECH bit
in the AD_CR Configuration Register.
The A/D peripheral converts the input voltage with
a process of successive approximations using a
fixed clock frequency derived from the 10 MHz
internal oscillator, divided by a factor that depends
on the speed mode: about 1.6 MHz in Fast Mode
and 800 kHz in Slow Mode. The speed mode is
chosen by theSCK bit ofthe AD_CR Configuration
Register.
The conversion range is found between theanalog
V
SS
and the A/D V
REF
references. The V
REF
can
be eitherinternal, derived from the V
DD
, or external
by using the VREF pin. The external reference
voltage allows the application of more precise and
stable reference voltages. The two modes are
selected by using the REF bit of the AD_CR
Configuration Register.
To
speed-up
the
Remark:
the voltageapplied to theVREF pin must
be in the range V
SS
-V
DD
.
The external reference voltage V
REF
is applied to
the analog pin PB0. This pin shares the alternate
functions with the first analog channel Ain0: if the
external reference mode is chosen the Ain0
CONFIGURATION REGISTERS
CONTROL
LOGIC
ANALOG
MUX
Ain0
Ain1
Ain2
Ain3
Ain4
Ain5
Ain6
Ain7
VREF
VDD
AUTO-ZERO /
AUTO-CALIBRATION
COMPARATOR
SUCCESSIVE
APPROXIMATION
REGISTER
SAMPLE
&
HOLD
DAC
RESISTIVE
REFERENCE
LADDER
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
STATUS REGISTER
INPUT REGISTERS
V
REF
SUCCESSIVE APPROXIMATION A/D CONVERTER
INT1
REF
CH0
CH1
CH2
: 6
: 12
Internal
Oscillator
10 MHz
A/D
clock
SCK
SEQ
POW
STR
CONT
INT0
RESOL
PRECH
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