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參數(shù)資料
| 型號(hào)： | ST52F514F3M6 |
| 英文描述： | IC MAX 7000 CPLD 256 256-FBGA |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 58/106頁(yè) |
| 文件大?。?/td> | 648K |
| 代理商： | ST52F514F3M6 |
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ST52F510/F513/F514
58/106
Example 1
:
IF Input
1
IS NOT Mbf
1
AND Input
4
is Mbf
12
OR Input
3
IS Mbf
8
THEN Crisp
1
is codified by the following instructions:
ISNOT 1 1
calculates the NOT
α
value of Input
1
with Mbf
1
and stores the result in internal registers
Example 2
, the priority of the operator is fixed by the brackets:
IF (Input
3
IS Mbf
1
AND Input
4
IS NOT Mbf
15
) OR (Input
1
IS Mbf
6
OR Input
6
IS NOT Mbf
14
) THEN Crisp
2
At the end of the fuzzy rules related to the current Fuzzy Variable, by using the instruction
OUT reg
, the
specified registeris written with the computed value. Afterwards,the control ofthe algorithm returns to the
CU. The next Fuzzy Variable evaluation must start again with a FUZZY instruction.
FZAND
implements the operation AND between the previous and the next alpha value evaluated
IS 4 12
fixes the
α
value of Input
4
with Mbf
12
and stores the result in internal registers
FZOR
implements the operation OR between the previous and the next alpha value evaluated
IS 3 8
fixes the
α
value of Input
3
with Mbf
8
and stores the result in internal registers
CON crisp
1
multiplies the result of the last
operation with the crisp value crisp
1
(
parenthesis open to change the priority
IS 3 1
fixes the
α
value of Input
3
with Mbf
1
and stores the result in internal registers
FZAND
implements the operation AND between the previous and the next alpha value evaluated
ISNOT 4 15
calculates the NOT
α
value of Input
4
with Mbf
15
and stores the result in internal registers
)
parenthesis closed
FZOR
implements the operation OR between the previous and the next alpha value evaluated
(
parenthesis open to change the priority
IS 1 6
fixes the
α
value of Input
1
with Mbf
6
and stores the result in internal registers
FZOR
implements the operation OR between the previous and the next alpha value evaluated
ISNOT 2 14
calculates the NOT
α
value of Input
6
with Mbf
14
and stores the result in internal registers
)
parenthesis closed
CON crisp
2
multiplies the result of the last
operation with the crisp value crisp
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST52F514G0B6 | IC MAX 7000 CPLD 256 256-FBGA |
| ST52F514G0M6 | IC MAX 7000 CPLD 64 100-TQFP |
| ST52F514G1B6 | IC MAX 7000 CPLD 64 100-TQFP |
| ST52F514G1M6 | IC MAX 7000 CPLD 64 44-PLCC |
| ST52F514G3B6 | IC MAX 7000 CPLD 64 44-TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52F514FMB6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI |
| ST52F514FMM6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI |
| ST52F514G0B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514G0M6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514G1B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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