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參數(shù)資料
| 型號(hào)： | ST52F514F1B6 |
| 英文描述： | IC MAX 7000 CPLD 160 100-TQFP |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 86/106頁 |
| 文件大?。?/td> | 648K |
| 代理商： | ST52F514F1B6 |
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ST52F510/F513/F514
86/106
Acknowledge may be enabled and disabled via
software.
The I
2
C interface address and/or general call
address can be selected via software.
The speed of the I
2
C interface may be selected
between Standard (0-100KHz) and Fast I
2
C (100-
400KHz).
14.3.3 SDA/SCL Line Control.
Transmitter mode the interface holds theclock line
low before transmission, in order to wait for the
microcontroller to write the byte in the Data
Register.
Receiver mode: the interface holds the clock line
low after reception to wait for themicrocontroller to
read the byte in the Data Register.
SCL frequency is controlled by a programmable
clock divider which depends on the I
2
C bus mode.
When the I
2
C cell is enabled, the SDA and SCL
pins must be configured as floating open-drainI/O.
The value of the external pull-up resistance used
depends on the application.
14.4 Functional Description
By default the I
2
C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
First, the interface frequency must be configured
using
the
related
bits
Registers.
of
the
Configuration
14.4.1 Slave Mode.
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
Figure 14.2 I
2
C Interface Block Diagram
DATA REGISTER
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER (OAR)
CLOCK CONTROL REGISTER (I2C_CCR)
STATUS REGISTER 1 (I2C_SR1)
CONTROL REGISTER (I2C_CR)
SDA
SCL
CONTROL LOGIC
STATUS REGISTER 2 (I2C_SR2)
INTERRUPT
CLOCK CONTROL
DATA CONTROL
SCL
SDA
相關(guān)PDF資料 |
PDF描述 |
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| ST52F514F1M6 | IC MAX 7000 CPLD 256 208-PQFP |
| ST52F514F3B6 | IC MAX 7000 CPLD 256 208-PQFP |
| ST52F514F3M6 | IC MAX 7000 CPLD 256 256-FBGA |
| ST52F514G0B6 | IC MAX 7000 CPLD 256 256-FBGA |
| ST52F514G0M6 | IC MAX 7000 CPLD 64 100-TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52F514F1M6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514F3B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514F3M6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514FMB6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI |
| ST52F514FMM6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI |
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