參數(shù)資料
型號(hào): ST52F514F1B6
英文描述: IC MAX 7000 CPLD 160 100-TQFP
中文描述: 微控制器
文件頁(yè)數(shù): 74/106頁(yè)
文件大?。?/td> 648K
代理商: ST52F514F1B6
ST52F510/F513/F514
74/106
PWM/Timer 0 Control Register 2 (PWM0_CR2)
Configuration Register 10 (0Ah) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-6: Not Used
Bit 5:
T0WAV
T0OUT Waveform
0: pulse (type2)
1: square (type1)
Bit 4-0:
T0PRESC
PWM/Timer 0 Prescaler
The PWM/Timer 0 clock is divided by a
factor equal to 2
T0PRESC
.
The maximum
value allowed for T0PRESC is 10000
(010h)
.
PWM/Timer 0 Control Register 3 (PWM0_CR3)
Configuration Register 11 (0Bh) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:
T0SYNC
PWM/Timer 0 Set/Reset mask
0: Set/Reset activated
1: Set/Reset masked
Bit 6: not used
Bit 5:
T1SYNC
PWM/Timer 1 Set/Reset mask
0: Set/Reset activated
1: Set/Reset masked
Bit 4:
T0CKS
PWM/Timer 0 Clock Source
0: Internal clock
1: External Clock from T0CLK
Bit 3-2:
STRSRC
PWM/Timer 0Startsignalsource
00: Internal from T0STRT bit
01: External from T0STRT pin
10: Both internal and external
Bit 3-2:
RESSRC
PWM/Timer 0 Reset source
00: Internal fromT0STRT bit
01: External from T0STRT pin
10: Both internal and external
Interrupt Polarity Register (INT_POL)
Configuration Register 1 (01h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-6: Not Used
Bit 5: See LVD Registers Description
Bit 4:
RESPOL
Reset signal polarity
0: Reset on low level/falling edge
1: Reset on high level/rising edge
Bit 3:
STRPOL
Start signal polarity
0: Start on high level/rising edge
1: Start on low level/falling edge
Bit 2-0: See Interrupt Registers Description
12.5.2 PWM/Timer 0 Input Registers.
PWM/Timer 0 Counter High Input Register
(PWM0_COUNT_IN_H)
Input Register 21 (015h) Read only
Reset Value: 0000 0000 (00h)
Bit 7-0:
T0CI15-8
PWM/Timer 0 Counter MSB
In this register the current value of the Timer 0
Counter MSB can be read.
7
4
0
-
-
T0WAV
T0PRESC
7
4
2
0
T0SYNC
-
T1SYNC T0CKS
STRSRC
RESSRC
7
0
-
-
LVD_EN RESPOL STRPOL POLPB
POLPA POLNMI
7
0
T0CI15
T0CI14
T0CI13
T0CI12
T0CI11
T0CI10
T0CI9
T0CI8
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