參數(shù)資料
型號(hào)： ST52F514F1B6
英文描述： IC MAX 7000 CPLD 160 100-TQFP
中文描述： 微控制器
文件頁(yè)數(shù)： 45/106頁(yè)
文件大?。?/td> 648K
代理商： ST52F514F1B6
ST52F510/F513/F514
45/106
6.3 Programmable Low Voltage Detector
The on-chip Programmable Low Voltage Detector
(PLVD) circuit prevents the processor from falling
into an unpredictable status if the power supply
drops below a certain level.
When Vdd drops below the detection level, the
PLVD causes an internal processor Reset that
remains active as long as Vdd remains below the
trigger level.
The PLVD resets the entire device except the
Power-on Detector and the PLVD itself.
The PLVD can be enabled/disabled at reset by
setting the Option Byte 2 (PLVD_CR) bits.
When Vdd increases above the Trigger Level, the
PLVD reset is deactivated and theuser program is
started from the beginning.
The detection levels are programmable by means
of the Option Byte 2 (PLVD_CR). There are three
levels for the PLVD falling voltages (2.9V, 3.4V,
3.9V) and for rising voltages (3.1V, 3.65V, 4.2V).
The hysteresis for each level are respectively 200
mV, 250 mV and 300 mV.
The PLVD circuit will only detect a drop if Vdd
voltage stays below the safe threshold for at least
5
μ
s before activation/deactivation of the LVD in
order to filter voltage spikes.
The PLVD function isn’t active when it is in HALT
mode.
6.4 Power Saving modes
There are two types of Power Saving modes:
WAIT and HALT mode. These conditions may be
entered by using the WAIT or HALT instructions.
6.4.1 Wait Mode.
Wait mode places the ICU in a
low power consumption status by stopping the
CPU. All peripherals and the watchdog remain
active. During WAIT mode the Interrupts are
enabled. The ICU remains in Wait mode until an
Interrupt or a RESET occurs, whereupon the
Program Counter jumps to the interrupt service
routine or, if a Reset occurs, to the beginning of the
user program.
6.4.2 Halt Mode.
Halt mode is the lowest ICU
power consumption mode, which is entered by
executing the HALT instruction. The internal
oscillator
is
turned
off,
processing
to
be
terminated,
operations of the on-chip peripherals. Halt mode
cannot be used when the watchdog is enabled. If
the HALT instruction is executed while the
watchdog system is enabled, it will be skipped
without modifying the normal CPU operations.
causing
all
internal
including
the
The ICU can exit Halt mode upon reception of an
NMI, a Port Interrupt or a Reset. The internal
oscillator (10 MHZ) is started and a delay period of
4.096 clock cycles is initiated, in order to allow the
oscillator to stabilize and to ensure that recovery
has taken place from the Reset state.
If the device has been configured to work with the
internal clock, the user program is started,
otherwise the Option Byte 7 (WAKEUP) is read
and another count is started before running the
user program. The count duration depends on the
contents of the Option Byte 7 (WAKEUP), that
works as prescaler, according to the follwing
formula:
This delay has been introduced in ordet to ensure
that the oscillator has become stable after it is
restarted.
After the start up delay, by exiting with the NMI or
a Port interrupt, the CPU restarts operations by
serving the associated interrupt routine.
Note:
if the Port Interrupt is masked, the ICU
doesn’t exit the Halt mode with this interrupt.
Figure 6.3 WAIT Flow Chart
Delay
4096
WAKEUP
1
+
(
)
Tclk
×
×
=
OSCILLATOR
PERIPHERALS CLOCK
CPUCLOCK
INTERRUPTS
ON
ON
OFF
ENAB.
WAITISTRUCTION
RESET
INTERRUPT
YES
NO
CPUCLOCK
ON
PROGRAMCOUNTER RESET
NO
JUMPTO INT. ROUTINE
CPUCLOCK
ON
NORMALPROGRAMFLOW
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST52F514F1M6 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Microcontroller
ST52F514F3B6 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Microcontroller
ST52F514F3M6 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Microcontroller
ST52F514FMB6 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI
ST52F514FMM6 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI
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