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參數(shù)資料
| 型號(hào)： | ST52F514F0B6 |
| 英文描述： | IC MAX 7000 CPLD 128 144-TQFP |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 68/106頁 |
| 文件大?。?/td> | 648K |
| 代理商： | ST52F514F0B6 |
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ST52F510/F513/F514
68/106
11 WATCHDOG TIMER
11.1 Functional Description
The Watchdog Timer (WDT) is used to detect the
occurrence of a software fault, usually generated
by external interference or by unforeseen logical
conditions, which causes the application program
to abandon its normal sequence. The WDT circuit
generates an ICU reset on expiryof a programmed
time period, unless the program refreshes the
WDT before the end of the programmed time
delay. Sixteen different delays can be selected by
using the WDT configuration register.
After the end of the delay programmed by the
configuration register, if the WDT is active, it starts
a reset cycle pulling the reset signal low.
Once the WDT is activated, the application
program has to refresh the counter (by the
WDTSFR instruction) during normal operation in
order to prevent an ICU reset.
In ST52F510/F513/F514 devices it is possible to
choose
between
“Hardware”
Watchdog.
The
Hardware
counting to avoid unwanted stops for external
interferences. The first mode is always enabled
unless the Option Byte 4 (WDT_EN) is written with
a special code (10101010b): only this code can
switch the WDT in “Software” Mode, the other 255
possibilities keep the “Hardware” Mode enabled.
When the software mode is enabled, it is possible
to stop the WDT during the user program
executions by using the WDTSLP instruction.
When the WDT is in Hardware Mode, neither the
WDTSLP instruction nor external interference can
stop the counting. The “Hardware” WDT is always
enabled after a Reset.
or
“Software”
allows
WDT
the
Figure 11.1 Watchdog Block Diagram
The working frequency of WDT (PRES CLK in the
Figure 11.1) is equal to theclock master. The clock
master is divided by 500, obtaining the WDT CLK
signal that is used to fix the timeout of the WDT.
According to the WDT_CR Configuration Register
values, a WDT delay between 0.1ms and 937.5ms
can bedefined when the clock masteris 5 MHz. By
changing the clock master frequency the timeout
delay
can
be
calculated
configuration register values. The first 4 bits of the
WDT_CR register are used, obtaining 16 different
delays.
according
to
the
11.2 Register Description
SW Watchdog Enable (WDT_EN)
Option Byte 4 (04h)
Reset Value: 0000 0000 (00h)
Bit 7-0:
WDTEN7-0
SW Watchdog Enable byte
Writing the code 10101010 in this byte the
Software Watchdog mode is enabled.
D0
D1
D2
D3
Configuration
Register
RESET
WDTRFR
PRES CLK = CLK MASTER
WDTSLP
PRESCALER
WDT
RESET
GENERATOR
RESET
WTD CLK
Table 11.1 Watchdog Timing Range (5 MHz)
WDT timeout period (ms)
min
0.1
max
937.5
7
0
WDTEN7 WDTEN6 WDTEN5 WDTEN4 WDTEN3 WDTEN2 WDTEN1WDTEN0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ST52F514F0M6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514F1B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514F1M6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514F3B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| ST52F514F3M6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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