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參數(shù)資料
| 型號： | SST89C58RC-40-I-TQJE |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 63/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT FLASH 40TQFP |
| 標準包裝： | 160 |
| 系列： | FlashFlex® |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | EBI/EMI，I²C，SMBus，UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 2K x 8 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
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2011 Silicon Storage Technology, Inc.
DS25100A
12/11
66
FlashFlex MCU
SST89C58RC
Data Sheet
A Microchip Technology Company
Reset
A system reset initializes the MCU and begins program execution at program memory location 0000H
or the boot vector address. The reset input for the device is the RST pin. In order to reset the device, a
logic level high must be applied to the RST pin for at least two machine cycles (24 clocks), after the
oscillator becomes stable. ALE and PSEN# are weakly pulled high during reset. During reset, ALE and
PSEN# output a high level in order to perform a proper reset. This level must not be affected by exter-
nal element. A system reset will not affect the 512 Bytes of on-chip RAM while the device is running,
however, the contents of the on-chip RAM during power up are indeterminate. Following reset, all Spe-
cial Function Registers (SFR) return to their reset values outlined in Tables 4 to 8.
Power-on Reset
At initial power up, the port pins will be in a random state until the oscillator has started and the internal
reset algorithm has weakly pulled all pins high.
When power is applied to the device, the RST pin must be held high long enough for the oscillator to
start up (usually several milliseconds for a low frequency crystal), in addition to two machine cycles for
a valid power-on reset. An example of a method to extend the RST signal is to implement a RC circuit
by connecting the RST pin to VDD through a 10 F capacitor and to VSS through an 8.2K resistor as
shown in Figure 24. Note that if an RC circuit is being used, provisions should be made to ensure the
VDD rise time does not exceed 1 millisecond and the oscillator start-up time does not exceed 10 milli-
seconds.
For a low frequency oscillator with slow start-up time the reset signal must be extended in order to
account for the slow start-up time. This method maintains the necessary relationship between VDD and
RST to avoid programming at an indeterminate location. The POF flag in the PCON register is set to
indicate an initial power up condition. The POF flag will remain active until cleared by software. Please
refer to Section 3.5, PCON register definition, for detailed information.
For more information on system level design techniques, please review the Design Considerations
for the SST FlashFlex Family Microcontroller application note.
Figure 24:Power-on Reset Circuit
1323 F48.0
VDD
10F
+
-
8.2K
SST89C58RC
RST
XTAL2
XTAL1
C1
C2
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