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參數(shù)資料
| 型號： | SST89C58RC-40-I-TQJE |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 48/88頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT FLASH 40TQFP |
| 標準包裝： | 160 |
| 系列： | FlashFlex® |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | EBI/EMI，I²C，SMBus，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 2K x 8 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
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2011 Silicon Storage Technology, Inc.
DS25100A
12/11
52
FlashFlex MCU
SST89C58RC
Data Sheet
A Microchip Technology Company
In slave mode, STO is set to recover SMBus from an error condition or generate a internal STOP for a
forced access to the bus. No STOP condition will be transmitted on the bus and the hardware behaves
as if a STOP condition has been received, SMBUS switches to “not addressed” slave receiver mode.
STO bit is cleared by hardware after one system clocks. STO bit can not be set when SMBEN is zero.
The Serial Interrupt flag (SI_0, SM0CON0.4) can be set in any possible SMBus status except for status
“0xD0” and status “0xF8. If EA and ES1 bits are set, an interrupt will requested when SI is set. When
SI flag is set by hardware, the SCL line is held to LOW until it is cleared by software (except for the sta-
tus “0xD0”, which will not hold the SCL line low). Only “0” can be written to clear SI flag, writing “1” has
no effect to the flag. When SI flag is cleared, SMBSTA register changes to “0xF8”.
During the acknowledge clock cycle on the SCL line, the Assert Acknowledge flag (AA_0,
SM0CON0.3) sets the level of the SDA line.
In slave transmitter mode, the AA flag is used to determine whether the last data byte will be transmit-
ted or enables whether to respond its slave address or general call address.
In master receiver mode, the AA flag is used to determine to return ACK or NACK after receiving a
byte. In slave receiver mode, the AA flag is used to determine to return ACK or NACK and enables
whether to respond its slave address or general call address.
1 = When set to 1, an acknowledge (low level to SDA) will be returned during the acknowledge clock
pulse on the SCL line on the following situations:
1.
The “own slave address” has been received.
2.
The general call address has been received while the general call bit (GC) in SMBADR is
set.
3.
A data byte has been received while the SMBUS interface is in the Master Receiver Mode.
4.
A data byte has been received while the SMBUS interface is in the addressed Slave
Receiver Mode.
0 = When cleared to 0, an non-acknowledge (high level to SDA) will be returned during the acknowl-
edge clock pulse on the SCL line on the following situations:
1.
A data byte has been received while the SMBUS interface is in the Master Receiver Mode.
2.
A data byte has been received while the SMBUS interface is in the addressed Slave
Receiver Mode.
To enable the SMBus Free Timeout feature, set the SMBus Free Timer Enable bit (FTE, SM0CON0.2)
to logic ‘1’. The bus is considered free and, if pending, a Start is generated when SCL and SDA remain
high for the SMBus Free Timeout given in the SMBUS Clock Rate Register.
To enable monitoring SCL low timeout function, set the SMBus Time out Enable bit (TOE_0,
SM0CON0.1) to logic ‘1’. When TOE is set, SMBUS will control the TIMER1 to count during the every
SCL low period. At every SCL falling-edge of the SCL, a reload counter pulse is generated to TIMER1;
at every SCL rising-edge of the SCL, a count stop pulse is generated to TIMER1. If the TIMER1’s
counter is reloaded and counting, the latest count stop pulse will cause the TIMER1 to generate an
interrupt for SCL low timeout.
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