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參數(shù)資料
| 型號： | SST89C58RC-40-I-TQJE |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 43/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT FLASH 40TQFP |
| 標準包裝： | 160 |
| 系列： | FlashFlex® |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | EBI/EMI，I²C，SMBus，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 2K x 8 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
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2011 Silicon Storage Technology, Inc.
DS25100A
12/11
48
FlashFlex MCU
SST89C58RC
Data Sheet
A Microchip Technology Company
On reset, SADDR and SADEN are “0”. This produces an given address of all “don’t cares” as well as a
broadcast address of all “don’t cares.” This effectively disables Automatic Addressing mode and allows
the micro controller to function as a standard 8051, which does not make use of this feature.
Enhanced SMBus Interface
The SST89C58RC includes two enhanced SUBus interfaces. The enhanced SMBus uses two wires
(SDA and SCL) to transfer information between devices connected to the bus.
SUBus Features
Only two lines required (SDA and SCL)
Master and slave modes
7-bit slave address support
Supports 0-400 Kbit data transfer speed
SCL line low duration time-out
Bus idle state detection interrupt
SCL configurable duty cycle
SDA line hold time configuration
SMBus Description
The SST89C58RC complies with the System Management Bus Specification, version 2.0. Reads and
writes are byte oriented with the SMBus interface to independently control the serial transfer of data
from the system controller to the interface. See figure 6-4 for a typical SMBus configuration.
By using the system clock as the bit rate clock source, data is transferred at speeds up to 400 Kbits per
second as a master or a slave. However, when using the TIMER1 as the bit rate clock source, data
transfer is reduced to speeds only up to 200 Kbits. These data transfer speeds are faster than those
specified by the SMBus specifications.
A typical SMBus configuration is shown in Figure 20 and Figure 21 shows how data transfer is accom-
plished on the bus.
Figure 20:Typical SMBus Configuration
1323 F44.0
P1.7/SDA
P1.6/SCL
SST89C58RC
with SMBus
Other Device
with SMBus
Interface
RP
VDD
SMBus
SDA
SCL
Other Device
with SMBus
Interface
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