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參數(shù)資料
| 型號(hào)： | SSD1818AZ |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LCD Segment / Common Driver with Controller |
| 中文描述： | LCD段/驅(qū)動(dòng)器與控制器通用 |
| 文件頁(yè)數(shù)： | 23/47頁(yè) |
| 文件大小： | 642K |
| 代理商： | SSD1818AZ |
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SSD1818A
Rev 1.2
P 23/47 Mar 2004
Solomon Systech
8. COMMAND TABLE
Table 5 - Write Command Table (
D/
C
=0, R/
W
(
WR
)=0,
E(
RD
)
=1)
D/C
0
Hex
00 – 0F
D7 D6 D5 D4 D3
0
0
0
D2
X
2
D1
X
1
D0
X
0
Command
Set Lower
Column
Address
Description
0
X
3
Set the lower nibble of the column address
register using X
3
X
2
X
1
X
0
as data bits. The lower
nibble of column address is reset to 0000b after
POR.
Set the higher nibble of the column address
register using X
3
X
2
X
1
X
0
as data bits. The higher
nibble of column address is reset to 0000b after
POR.
Feedback gain of the internal regulated DC-DC
converter for generating VOUT increases as
X
2
X
1
X
0
increased from 000b to 111b. After POR,
X
2
X
1
X
0
= 100b.
X
0
=0: turns off the output op-amp buffer (POR)
X
0
=1: turns on the output op-amp buffer
X
1
=0: turns off the internal regulator (POR)
X
1
=1: turns on the internal regulator
X
2
=0: turns off the internal voltage booster (POR)
X
2
=1: turns on the internal voltage booster
Set GDDRAM display start line register from 0-63
using X
5
X
4
X
3
X
2
X
1
X
0
.
Display start line register is reset to 000000 after
POR.
Select contrast level from 64 contrast steps.
Contrast increases (VL6 decreases) as
X
5
X
4
X
3
X
2
X
1
X
0
is increased from 000000b to
111111b. X
5
X
4
X
3
X
2
X
1
X
0
= 100000b after POR.
X
0
=0: column address 00h is mapped to SEG0
(POR)
X
0
=1: column address 67h is mapped to SEG0
Refer to Table 4 on page 20 for example.
X
0
=0: POR default bias
48 MUX Mode: 1/8
54 MUX Mode: 1/8.4
32 MUX Mode: 1/6
64 MUX Mode: 1/9
X
0
=1: alternate bias
48 MUX Mode: 1/6
54 MUX Mode: 1/6
32 MUX Mode: 1/5
64 MUX Mode: 1/7
For other bias ratio settings, see “Set 1/4 Bias
Ratio” and “Set Bias Ratio” in Extended Command
Set.
0
0
0
0
1
X
3
X
2
X
1
X
0
10 – 1F
Set Higher
Column
Address
0
20 – 27
0
0
1
0
0
X
2
X
1
X
0
Set Internal
Gain Resistor
Ratio
0
28 – 2F
0
0
1
0
1
X
2
X
1
X
0
Set Power
Control
Register
0
1
X
5
X
4
X
3
X
2
X
1
X
0
0
40 – 7F
Set Display
Start Line
0
0
81
1
*
0
*
0
X
5
X
4
0
0
X
3
0
X
2
0
X
1
1
X
0
00 – 3F
Set Contrast
Control
Register
0
A0 – A1
1
0
1
0
0
0
0
X
0
Set Segment
Re-map
0
A2 – A3
1
0
1
0
0
0
1
X
0
Set LCD Bias
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