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Solomon Systech
Mar 2004
P 16/47 Rev 1.2
SSD1818A
Read cycle
E(RD ) input serves as data read latch signal (clock) when low, provided that
CS2 is pulled high respectively. The D
/
C
signal determines whether the receiving signal is a display data
read or a status register read signal. Similar to 6800-series interface, a dummy read is also required
before the first actual display data read.
1
CS is pulled low and the
Write cycle
R/
W
( WR ) input serves as data write latch signal (clock) when high, provided that
and high respectively. The D
/
C
signal determines whether the receiving signal is a display data write or a
command register write signal.
Please refer to Figure 10 on Page 39 for Parallel Interface Timing Diagram of 8080-series microprocessor.
1
CS and CS2 are low
MPU Serial interface
The serial interface consists of serial clock SCK (D
6
), serial data SDA (D
7
), D
/
C
,
SDA is shifted into a 8-bit shift register on every rising edge of SCK in the order of D
7
, D
6
,... D
0
. D
/
C
is
sampled on every eighth clock to determine whether the data byte in the shift register is written to the
Display Data RAM or command register at the same clock.
1
CS and CS2. Input to
Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry (Figure 4). The oscillator generates the clock
for the DC-DC voltage converter. This clock is also used in the Display Timing Generator.
enable
Oscillation Circuit
enable
Buffer
Internal resistor
OSC2
OSC1
Oscillator
enable
(CL)
Figure 4 - Oscillator
LCD Driving Voltage Generator and Regulator
This module generates the LCD voltage required for display driving output. With reference to V
DD
, it takes
a single supply input, V
SS
, and generates necessary voltage levels. This block consists of:
1. 2X, 3X, 4X and 5X DC-DC voltage converter
The built-in DC-DC voltage converter is used to generate the negative voltage with reference to VDD from
the voltage input (VSS1). For SSD1818A, it is possible to produce 2X, 3X, 4X or 5X boosting from the
potential different between V
SS1
- V
DD
. Detailed configurations of the DC-DC converter for different
boosting multiples are given in Figure 5.