參數(shù)資料
型號: SSD1818ATR1
廠商: Electronic Theatre Controls, Inc.
英文描述: LCD Segment / Common Driver with Controller
中文描述: LCD段/驅(qū)動器與控制器通用
文件頁數(shù): 15/47頁
文件大?。?/td> 642K
代理商: SSD1818ATR1
SSD1818A
Rev 1.2
P 15/47 Mar 2004
Solomon Systech
7. FUNCTIONAL BLOCK DESCRIPTIONS
Command Decoder and Command Interface
This module determines whether the input signal is interpreted as data or command. Input is directed to
this module based on the input of the D/C pin.
If the D/
C
pin is high, input is written to Graphic Display Data RAM (GDDRAM). If it is low, the input at
D
7
-D
0
is interpreted as a Command. It will be decoded and written to the corresponding command register.
MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D
7
-D
0
), R/
W
(
WR
), D/C , E/(
RD
),
CS2.
1
CS and
Read cycle
R/
W
( WR ) input high indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the
status register. In order to match the operating frequency of the GDDRAM with that of the MCU, pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual
display data read. This is shown in Figure 3.
data bus
Figure 3 - Display Data Read Back Procedure - Insertion of Dummy Read
Write cycle
R/
W
(
WR
) input Low indicates a write operation to Display Data RAM or Internal Command Registers
depending on the
D/
C
input. The E(RD ) input serves as data latch signal (clock) when high, provided that
1
CS is pulled low and the CS2 is pulled high respectively.
Please refer to Figure 9 on Page 38 for Parallel Interface Timing Diagram of 6800-series microprocessors.
MPU Parallel 8080-series interface
The parallel interface consists of 8 bi-directional data pins (D
7
-D
0
), E/(
RD
), R/
W
(
WR
), D/C ,
CS2.
1
CS and
R/W
(WR)
E(RD)
write column address
dummy read
data read1
data read 2
data read 3
N
n
n+1
n+2
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