參數資料
型號： SSD1815T3R
廠商： Electronic Theatre Controls, Inc.
英文描述： SEMICONDUCTOR TECHNICAL DATA
中文描述： 半導體技術數據
文件頁數： 9/35頁
文件大?。?/td> 856K
代理商： SSD1815T3R
S OLOMON
SSD1815
9
REV 1.5
03/2000
Oscillation Circuit
enable
OSC1
OSC2
Internal pwell resistor
Oscillator enable
Buffer
enable
(CL)
Figure 4 - Oscillator Circuitry
OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER
Description of Block Diagram Module
R/W(WR)
E(RD)
N
n
n+1
n+2
data bus
write column address
dummy read
data read1
data read 2
data read 3
Figure 3 -
Display data read with the insertion of dummy read
Command Decoder and Command Interface
This module determines whether the input data is interpreted as
data or command. Data is directed to this module based upon the
input of the D/C pin. If D/C is high, data is written to Graphic Display
Data RAM (GDDRAM). If D/C is low, the input at D
7
-D
0
is interpreted
as a Command and it will be decoded and be written to the corre-
sponding command register.
MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D
7
-D
0
),
R/W(WR), D/C, E(RD), CS1 and CS2. R/W(WR) input High indicates
a read operation from the Graphic Display Data RAM (GDDRAM) or
the status register. R/W(WR) input Low indicates a write operation to
Display Data RAM or Internal Command Registers depending on the
status of D/C input. The E(RD) input serves as data latch signal
(clock) when high provided that CS1 and CS2 are low and high
respectively. Refer to Figure 9 for Parallel Interface Timing Diagram
of 6800-series microprocessors.
In order to match the operating frequency of display RAM with that
of the microprocessor, some pipeline processing is internally per-
formed which requires the insertion of a dummy read before the first
actual display data read. This is shown in Figure 3 below.
MPU Parallel 8080-series interface
The parallel interface consists of 8 bi-directional data pins (D
7
-D
0
),
E(RD), R/W(WR), D/C, CS1 and CS2. E(RD) input serves as data
read latch signal (clock) when low provided that CS1 and CS2 are
low and high respectively. Whether it is display data or status regis-
ter read is controlled by D/C. R/W(WR) input serves as data write
latch signal(clock) when high provided that CS1 and CS2 are low
and high respectively. Whether it is display data or command regis-
ter write is controlled by D/C. Refer to Figure 10 for Parallel Interface
Timing Diagram of 8080-series microprocessor.
Similar to 6800-series interface, a dummy read is also required
before the first actual display data read.
MPU Serial interface
The serial interface consists of serial clock SCK (D
6
), serial data
SDA (D
7
), D/C, CS1 and CS2. SDA is shifted into a 8-bit shift register
on every rising edge of SCL in the order of D
7
, D
6
,... D
0
. D/C is sam-
pled on every eighth clock to determine whether the data byte in the
shift register is written to the Display Data RAM or command register
at the same clock.
Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry
(Figure 4). The oscillator generates the clock for the DC-DC volt-
age converter. This clock is also used in the Display Timing Gen-
erator.
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參數描述
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