參數(shù)資料
型號(hào): SSD1800
廠商: Electronic Theatre Controls, Inc.
英文描述: LCD Segment / Common Driver with Controller
中文描述: LCD段/驅(qū)動(dòng)器與控制器通用
文件頁(yè)數(shù): 15/42頁(yè)
文件大?。?/td> 598K
代理商: SSD1800
SSD1800 Series
Rev 1.0
P 15/42 Mar 2004
Solomon Systech
8
FUNCTIONAL BLOCK DESCRIPTIONS
8.1 Command Decoder and Command Interface
This module determines whether the input data is interpreted as data or command. Data is directed to this module
based upon the input of the D/C pin. If D/C is high, data is written to internal memories (DDRAM, CGRAM,
ICONRAM). If D/C is low, the input at D
7
-D
0
is interpreted as a Command and it will be decoded and be written to
the corresponding command register.
8.2 MPU Parallel 6800-series Interface in 8 bits bus mode
The parallel interface consists of 8 bi-directional data pins (D
7
-D
0
), R/W (
WR
), D/C , E(
RD
),CS. R/W (
WR
)
input high indicates a read operation from the internal RAM (DDRAM, CGRAM and ICONRAM). R/W (
WR
) input low
indicates a write operation to internal RAM (DDRAM, CGRAM and ICONRAM) or Internal Command Registers
depending on the status of D/C input. The E(
RD
) input serves as data latch signal (clock) when high provided that
CS are low. Refer to Figure 20 for Parallel Interface Timing Diagram of 6800-series microprocessors.
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processings are internally performed which require the insertion of a dummy read before the first actual display data
read. This is shown in Figure 4 below. The dummy read make the address counter (AC) increased by 1. So it is
recommended to set address again before writing. The consecutive read after the dummy read are also the valid
data. The instruction read cycle is not supported and it is regarded as a no operation cycle.
8.3 MPU Parallel 8080-series Interface in 8 bits bus mode
The parallel interface consists of 8 bi-directional data pins (D
7
-D
0
), R/W (
WR
), D/C , E(
RD
),CS. E(
RD
) input
serves as data read latch signal (clock) when low provided that CS is low whether it is Command write or internal
RAM read/ write is controlled by D/C . R/W (
WR
) input serves as data write latch signal (clock) when low provided
that CS is low. Refer to Figure 21 for Parallel Interface Timing Diagram of 8080-series microprocessor.
Similar to 6800-series interface, a dummy read is also required before the first actual display data read.
8.4 4-bit MPU Parallel 6800/8080-Series Interface
The control of 4-bit bus mode is exactly the same as 8-bit bus mode except 2 consecutive access (read/ write) is
needed to read/ write 8 bits data. For write operation, upper order bits are written before the low order bits, and low
order bits are always read before the upper order bit in read transaction.
8.5 MPU Serial Interface
The serial interface consists of serial clock SCK (D
6
), serial data SDA (D
7
), D/C , CS. SDA is shifted into a 8-bit
shift register on every rising edge of SCK in the order of D
7
, D
6
, ... D
0
. D/C is sampled on every eighth clock to
determine whether the data byte in the shift register is written to the internal RAM (DDRAM, CGRAM, ICONRAM) or
command register at the same clock.
8.6 Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry. The oscillator generates the clock for the DC-DC
voltage converter. This clock is also used in the Display Timing Generator.
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