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參數(shù)資料
型號(hào): DG406DW-E3
廠商: Vishay Siliconix
文件頁數(shù): 2/16頁
文件大?。?/td> 0K
描述: IC MULTIPLEXER 16X1 28SOIC
標(biāo)準(zhǔn)包裝: 250
功能: 多路復(fù)用器
電路: 1 x 16:1
導(dǎo)通狀態(tài)電阻: 100 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 12V,±5 V ~ 20 V
電流 - 電源: 30µA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 管件
產(chǎn)品目錄頁面: 1132 (CN2011-ZH PDF)
DG406, DG407
www.vishay.com
Vishay Siliconix
S13-2518-Rev. K, 09-Dec-13
10
Document Number: 70061
For technical questions, contact: analogswitchsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
APPLICATIONS HINTS
Sampling speed is limited by two consecutive events: the
transition time of the multiplexer, and the settling time of the
sampled signal at the output.
tTRANS is given on the data sheet. Settling time at the load
depends on several parameters: RDS(on) of the multiplexer,
source impedance, multiplexer and load capacitances,
charge injection of the multiplexer and accuracy desired.
The settling time for the multiplexer alone can be derived
from the model shown in figure 5. Assuming a low
impedance signal source like that presented by an op amp
or a buffer amplifier, the settling time of the RC network for
a given accuracy is equal to n
:
Fig. 5 - Simplified Model of One Multiplexer Channel
The maximum sampling frequency of the multiplexer is:
(1)
where N = number of channels to scan
tSETTLING = n = n x RDS(on) x CD(on)
For the DG406 then, at room temp and for 12-bit accuracy,
using the maximum limits:
(2)
or
(3)
From the sampling theorem, to properly recover the original
signal, the sampling frequency should be more than twice
the maximum component frequency of the original signal.
This assumes perfect bandlimiting. In a real application
sampling at three to four times the filter cutoff frequency is
a good practice.
Therefore from equation 2 above:
(4)
From this we can see that the DG406 can be used to sample
16 different signals whose maximum component frequency
can be as high as 173 kHz. If for example, two channels are
used to double sample the same incoming signal then its
cutoff frequency can be doubled.
The block diagram shown in figure 6 illustrates a typical data
acquisition front end suitable for low-level analog signals.
Differential multiplexing of small signals is preferred since
this method helps to reject any common mode noise. This
is especially important when the sensors are located at a
distance and it may eliminate the need for individual
amplifiers. A low RDS(on), low leakage multiplexer like the
DG407 helps to reduce measurement errors. The low power
dissipation of the DG407 minimizes on-chip thermal
gradients which can cause errors due to temperature
mismatch along the parasitic thermocouple paths. Please
refer to Application Note AN203 for additional information.
Fig. 6 - Measuring Low-Level Analog Signals is more accurate when using a Differential Multiplexing Technique
reliability data, see www.vishay.com/ppg?70061.
% ACCURACY
# BITS
N
0.25
8
6
0.012
12
9
0.0017
15
11
RS = 0
RDS(on)
VOUT
CD(on)
f
s
1
Nt
SETTLING
t
TRANS
+
-------------------------------------------------------------
=
f
s
1
16 9
100
10
- 12
F
300 10
- 12
s
+
---------------------------------------------------------------------------------------------------------
=
f
s
694 kHz
=
f
c
1
4
---
f
s
173
=
kHz
=
12-Bit
A/D
Converter
Analog
Multiplexer
DG407
Controller
To
Sensor 1
To
Sensor 8
Inst
Amp
S/H
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