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參數(shù)資料
| 型號(hào)： | SSD1702 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 240-outputs LCD driver |
| 中文描述： | 240 - LCD驅(qū)動(dòng)輸出 |
| 文件頁(yè)數(shù)： | 21/47頁(yè) |
| 文件大?。?/td> | 586K |
| 代理商： | SSD1702 |
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SSD1702
Rev 1.1
P 21/46 Dec 2003
Solomon Systech
Pin Name
SEGMENT MODE
COMMON MODE
FR
FR is the AC signal input for LC driving waveform. Normally it is the frame inversion
signal.
The input signal is level-shifted from logic voltage level to LC driving voltage level to
control the LC driving circuit.
The output voltage of the LC driver output pins are set by
the line latch / shift register output signal and the FR signal. Their relationship is shown
in Table 6 and Table 7.
EIO1, EIO2
These are the I/O pins for chip selection.
When L/R is set to L, EIO1 will be the
output and EIO2 will be the input.
When L/R is set to H, EIO1 will be the
input and EIO2 will be the output.
After an LP signal is input and the
EIO(input) is set to L, the chip will be
selected.
It
will
automatically after reading 240 bits of
data.
be
deselected
EIO(output) is normally H. It will only be
pull L for one XCK cycle (from falling edge
to falling edge of XCK) when 240 bits of
data have been read.
Refer to Figure 10 for details timing.
These are the bi-directional shift register
shift data I/O pin.
When L/R is set to L, EIO1 will be the
output and EIO2 will be the input.
When L/R is set to H, EIO1 will be the
input and EIO2 will be the output.
A YD signal (Vertical scanning start pulse)
is expected at the EIO(input). A H level at
EIO(input) during LP falling edge indicates
the start of a vertical frame.
Refer to Figure 11 for details timing.
Y1-Y240
These are LC driver output pins. The output level can be referred Table 6 and Table 7.
Note:
Logic H means VDD level
Logic L means VSS level
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