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參數(shù)資料
| 型號： | SSD1339U3 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 132RGB x 132 with 2 smart Icon lines Dot Matrix OLED/PLED Segment/Common Driver with Controller |
| 中文描述： | 132RGB × 132 2智能圖標(biāo)行點(diǎn)陣的OLED /短差段/驅(qū)動(dòng)器與控制器通用 |
| 文件頁數(shù)： | 30/59頁 |
| 文件大?。?/td> | 916K |
| 代理商： | SSD1339U3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁
Solomon Systech
Jul 2005
P 30/59 Rev 1.1
SSD1339
D/C Hex
D7 D6 D5 D4 D3 D2 D2 D0
Command
Description
0
A2
1
0
1
0
0
0
1
0
Set vertical scroll by Row from 0-131. [reset=00b]
1
A[7:0]
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Set Display Offset
0
A4~A7
1
0
1
0
0
1
X
1
X
0
A4: All Off
A5: All On (All pixels have GS15)
A6 : Reset to normal display (POR)
A7: Inverse Display (GS0 -> GS63, GS1 -> GS62, ....)
Set Display Mode
0
AD
1
0
1
0
1
1
0
1
A[7:0] should be set as 100011A[1]A[0]b
1
A[7:0]
1
0
0
0
1
A
2
A
1
A
0
A[0]= 0 Select external VCC supply at master ON
A[0] = 1 Select internal booster at master ON [reset]
A[1]= 0 Select external VCOMH voltage supply at master
ON
A[1] = 1 Select internal VCOMH regulator at master ON
[reset]
A[2] = 0 Select external pre-charge voltage source
Master
Configuration
A[2] = 1 Select internal pre-charge voltage source [reset]
0
AE~AF
1
0
1
0
1
1
1
X
0
AE = Sleep mode On (Display off)
Set Sleep mode
On/Off
AF = Sleep mode Off (Display on)
0
B0
1
0
1
1
0
0
0
0
A[4:0]:
0
0
0
A
4
A
3
A
2
A
1
A
0
00000b = Normal
10010b = Power Saving
Power Saving
Mode
00101b = Reserved
0
B1
1
0
1
1
0
0
0
1
A[3:0] Phase 1 period of 1~16 dclk clocks [reset=4h]
1
A[7:0]
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A[7:4] Phase 2 period of 1~16 dclk clocks [reset=7h]
(Phase 2) period
Set Reset (Phase
1) /Pre-charge
0
B3
1
0
1
1
0
0
1
1
A[3:0] [reset=0], divide by DIVSET+1 (i.e. 1 to 16)
1
A[7:0]
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A[7:4] Osc frequency, frequency increase as level
increase [reset=1001b]
Front Clock Divider
(DivSet)/ Oscillator
Frequency
The next 32 bytes of command set the current drive
pulse width of gray scale level GS1, GS3, GS5 …GS63
as below in unit of DCLK.
A[7:0] : PW1, POR =1 DCLK
0
B8
1
0
1
1
1
0
0
0
1
A[7:0]
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
B[7:0] : PW3, POR = 5 DCLK
1
B[7:0]
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
C[7:0] : PW5, POR = 9 DCLK
1
.
.
.
.
.
.
.
.
.
.
1
.
.
.
.
.
.
.
.
.
.
1
.
.
.
.
.
.
.
.
.
AE[7:0] : PW61, POR = 121 DCLK
1
.AE[7:0] AE
7
AE
6
AE
5
AE
4
AE
3
AE
2
AE
1
AE
0
AF[7:0] : PW63, POR = 123 DCLK
1
AF[7:0] AF
7
AF
6
AF
5
AF
4
AF
3
AF
2
AF
1
AF
0
where
PW1 must > 0
Look Up Table for
Gray Scale Pulse
width
PW3 must > PW1+1
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