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參數(shù)資料
| 型號： | SSD1339U3 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 132RGB x 132 with 2 smart Icon lines Dot Matrix OLED/PLED Segment/Common Driver with Controller |
| 中文描述： | 132RGB × 132 2智能圖標行點陣的OLED /短差段/驅(qū)動器與控制器通用 |
| 文件頁數(shù)： | 24/59頁 |
| 文件大?。?/td> | 916K |
| 代理商： | SSD1339U3 |
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Solomon Systech
Jul 2005
P 24/59 Rev 1.1
SSD1339
The sequence of sending 65K color depth pixel in 8-bit MCU interface is divided into two 8-bit sessions as
shown below.
Bit
7
6
5
1
st
byte
C1
4
C1
3
C1
2
2
nd
byte
B1
2
B1
1
B1
0
4
3
2
1
0
C1
1
A1
4
C1
0
A1
3
B1
5
A1
2
B1
4
A1
1
B1
3
A1
0
Figure 15 – 65k color depth graphic display data writing sequence in 8-bit MCU interface
With reference to Figure 8 conventions, in writing the data into graphic display data RAM, the bit positions
filled by the input data for each color is shown below.
Color A
Bit Position
A5
A4
A3
Input Data
A1
4
A1
3
A1
2
Color B
Bit Position
B5
B4
B3
Input Data
B1
5
B1
4
B1
3
Color C
Bit Position
C5
C4
C3
Input Data
C1
4
C1
3
C1
2
A2
A1
1
A1
A1
0
A0
A1
4
B2
B1
2
B1
B1
1
B0
B1
0
C2
C1
1
C1
C1
0
C0
C1
4
Figure 16 – Display data RAM writing position for color A, B and C data input in 65k color mode
In data RAM, each data occupies 6-bit. However, color A and C have 5-bit length only in 65k color mode.
Therefore, RAM positions A0 and C0 are empty originally. These emptied positions are filled as shown
above to increase color A and C to 6-bit length in display data RAM.
Data access in 256 colors mode
In 256-color mode, each pixel is composed of 8-bit. Only 8-bit MCU interface is available to access
display data RAM. The communication session is done in 1 time by writing 8-bit data into RAM.
Bit
7
6
5
1
st
byte
C1
2
C1
1
C1
0
4
3
2
1
0
B1
2
B1
1
B1
0
A1
1
A1
0
Figure 11 – 256 Color Depth Graphic Display Data Writing Sequence in 8-bit MCU Interface
With reference to Figure 8 conventions, in writing the data into graphic display data RAM, the bit positions
filled by the input data for each color is shown below.
Color A
Bit Position
A5
A4
A3
Input Data
A1
1
A1
0
A1
1
A2
A1
1
A1
A1
1
A0
A1
1
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