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參數(shù)資料
| 型號： | SSD1339U3 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 132RGB x 132 with 2 smart Icon lines Dot Matrix OLED/PLED Segment/Common Driver with Controller |
| 中文描述： | 132RGB × 132 2智能圖標(biāo)行點(diǎn)陣的OLED /短差段/驅(qū)動(dòng)器與控制器通用 |
| 文件頁數(shù)： | 20/59頁 |
| 文件大小： | 916K |
| 代理商： | SSD1339U3 |
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Solomon Systech
Jul 2005
P 20/59 Rev 1.1
SSD1339
Command Decoder and Command Interface
This module determines whether the input data is interpreted as data or command. Data is interpreted
based upon the input of the D/C# pin.
If D/C# pin is high, data is written to Graphic Display Data RAM (GDDRAM). If it is low, the input at D
7
-D
0
is interpreted as a Command and it will be decoded and be written to the corresponding command
register.
MPU Parallel 6800-series Interface
The parallel interface consists of 18 bi-directional data pins (D
17
-D
0
) or 8 bi-directional data pins (D
7
-D
0
),
R/W#(WR#), D/C#, E (RD#) and CS#. R/W#(WR#) input High indicates a read operation from the Graphic
Display Data RAM (GDDRAM) or the status register. RW#/(WR#) input Low indicates a write operation to
Display Data RAM or Internal Command Registers depending on the status of D/C# input. The E(RD#)
input serves as data latch signal (clock) when high provided that CS# is low and high respectively. Refer
to .
Figure 32 of parallel timing characteristics for Parallel Interface Timing Diagram of 6800-series
microprocessors.
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual
display data read. This is shown in Figure 6 below.
n+2
n+1
Write column
address
Dummy read
Data read1
R/
W#(WR#)
Data bus
N
n
E(RD#)
Data read2
Data read3
Figure 6 – Display data read back procedure - insertion of dummy read
MPU Parallel 8080-series Interface
The parallel interface consists of 18 bi-directional data pins (D
17
-D
0
) or 8 bi-directional data pins (D
7
-D
0
), E
(RD#), R/W#(WR#), D/C# and CS#. The E(RD#) input serves as data read latch signal (clock) when low,
provided that CS# is low and high respectively. Display data or status register read is controlled by D/C#.
R/W#(WR#) input serves as data write latch signal (clock) when high provided that CS# is low and high
respectively. Display data or command register write is controlled by D/C#. Refer to * when 8 bit used: D
0
~ D
7
instead; when 9 bit used: D
0
~ D
8
instead; when 16 bit used: D
0
~ D
15
instead; when 18 bit used: D
0
~ D
17
instead.
Figure 33 of parallel timing characteristics for Parallel Interface Timing Diagram of 8080-series
microprocessor. Similar to 6800-series interface, a dummy read is also required before the first actual
display data read.
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