參數(shù)資料
型號: SSD1303Z
廠商: Electronic Theatre Controls, Inc.
英文描述: 132 x 64 Dot Matrix OLED/PLED Segment/Common Driver with Controller
中文描述: 132 × 64點陣的OLED /短差段/驅(qū)動器與控制器通用
文件頁數(shù): 21/56頁
文件大小: 586K
代理商: SSD1303Z
SSD1303
Rev 1.7
P 21/56 May 2005
Solomon Systech
8
COMMAND TABLE
Table 4 - Command table
(D/C =0, R/W (WR#)=0, E (RD#)=1)
Note: commands marked with “**” are compatible to SSD1301
D/C Hex
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
X
3
X
2
X
1
X
0
Command
Set Lower Column
Address **
Description
00~0F
Set the lower nibble of the column address register
using X
X
X
X
as data bits. The initial display line
register is reset to 0000b after POR.
0
10~1F
0
0
0
1
X
3
X
2
X
1
X
0
Set Higher Column
Address **
Set the higher nibble of the column address register
using X
X
X
X
as data bits. The initial display line
register is reset to 0000b after POR.
0
0
26
0
*
0
*
1
*
0
*
0
*
1
A
2
A
1
A
0
B
2
B
1
B
0
*
C
1
C
0
1
0
Horizontal scroll setup
A[2:0] Set the number of column scroll per step
Valid value: 001b, 010b, 011b, 100b
A[2:0]
0
0
B[2:0]
C[1:0]
*
*
*
*
*
*
*
*
*
*
B[2:0] Define start page address
C[1:0] Set time interval between each scroll step in
terms of frame frequency
0
D[2:0]
*
*
*
*
*
D
2
D
1
D
0
00b – 12 frame
01b – 64 frames
10b – 128 frames
11b – 256 frames
D[2:0] Define end page address
Activate horizontal scroll Start horizontal scrolling
Set the value of D[2:0] larger or equal to B[2:0]
0
0
0
1
0
1
1
1
1
2F
0
0
0
1
0
1
1
1
0
2E
Deactivate horizontal
scroll
Stop horizontal scrolling
Set display TAM display start line register from 0-63
using X
5
X
3
X
2
X
1
X
0
.
Display start line register is reset to 000000 during
POR
0
40-7F
0
1
X
5
X
4
X
3
X
2
X
1
X
0
Set Display Start Line
0
81
1
0
0
0
0
0
0
1
0
A[7:0]
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Set Contrast Control
Register **
Double byte command to select 1 out of 256 contrast
steps. Contrast increases as the value increases.
(POR = 80h)
Double byte command to select 1 out of 256
brightness steps. Brightness increases as the value
increases. (POR = 80h)
Set current drive pulse width of Bank 0, Colour A, B
and C.
0
82
1
0
0
0
0
0
1
0
0
A[7:0]
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Brightness for color
banks
0
91
1
0
0
1
0
0
0
1
0
X[5:0]
*
*
X
5
X
4
X
3
X
2
X
1
X
0
Bank 0: X[5:0] = 0… 63; for pulse width set to 1 ~
64 clocks (POR = 110001b)
0
A[5:0]
*
*
A
5
A
4
A
3
A
2
A
1
A
0
B
5
B
4
B
3
B
2
B
1
B
0
C
5
C
4
C
3
C
2
C
1
C
0
Colour A: A[5:0] same as above (POR = 111111b)
0
0
B[5:0]
C[5:0]
*
*
*
*
Colour B: B[5:0] same as above (POR = 111111b)
Colour C: C[5:0] same as above (POR = 111111b)
Note: colour D pulse width is fixed at 64 clocks
pulse .
Set Look Up Table
(LUT) for area colour
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