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參數(shù)資料
| 型號(hào)： | SPL61A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 80KB LCD Controller/Driver |
| 中文描述： | 80kb左右LCD控制器/驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 6/15頁(yè) |
| 文件大?。?/td> | 737K |
| 代理商： | SPL61A |
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SPL61A
5.5. LCD Controller/Driver
SPL61A contains total of 640 dots LCD controller and driver.
Programmers can set the LCD configuration (bias, duty, voltage
doubler) by writing to LCD control register ($20). Once the LCD
configuration is initialized, the desired pattern can be displayed by
filling the LCD buffer with appropriate data. The LCD driver can
also operate during sleep by keeping 32768 oscillator running.
The LCD driver in SPL61A is designed to fit most LCD
specifications. It can either be programmed as 1/4 or 1/5 bias
and the duty is also programmable as 1/8, 1/12, or 1/16 duty.
5.6. Voltage Doubler/Regulator
SPL61A also contains a built-in voltage doubler and a voltage
regulator. The voltage regulator provides a reference voltage
(HVLCD)
for
voltage
doubler
to
generate
VLCD
(by
charge-pumping). Users can get desired VLCD by changing the
output reference voltage (writing to $23) of the voltage regulator.
By enabling the voltage doubler and regulator, users can get a
stable VLCD that will not be affected by VDD. The three
possible configurations of voltage doubler and regulator are shown
in the following table.
Regulator
Doubler
VLCD
OFF
OFF
VDD (not regulated)
OFF
ON
2*VDD (not regulated)
ON
OFF
N/A
ON
ON
3.3V - 4.8V adjustable
5.7. PWM Output
Internally, SPL61A has one pair of PWM outputs with two sound
channels. Each channel can be set to play speech or tone
individually. SPL61A uses Pulse Width Modulation that could
directly drive speaker or buzzer without any buffer or amplification
circuit.
5.8. Asynchronous Serial Interface
SPL61A supports 1-channel UART for serial communications. It
supports bit rates up to 115.2kbps. UART operation is controlled
by UART command registers $29 and $2A. Configurations such
as Tx/Rx interrupt, parity check, parity even/odd and clock source
can be set in command registers. Two interrupts are generated
by Rx and Tx. The Rx or Tx interrupt asserts when a byte is
received or transmitted. By reading the status register $2A,
users can tell whether the interrupt is generated by Rx or Tx.
Framing, overrun and parity errors are detected as each byte is
received. All error status can be read from status register $2A.
The UART supports clock auto calibration. If this clocking
scheme is selected, standard baud rates from 1.2kbps to
115.2kbps are available. The baud rate is selected by writing to
baud rate control registers $2E and $2F. The supported standard
baud rates and their minimum R-oscillator clock frequency
required are shown in the following table.
Baud Rate(bps)
Min. Frosc(Hz)
1200
24000
2400
48000
4800
96000
9600
192000
19200
384000
38400
768000
51200
1024000
57600
1152000
102400
2048000
115200
2304000
If the auto calibration clocking scheme is not selected, users can
get desired baud rates by writing appropriate values to prescaler
registers, $2C and $2D. Non-standard baud rates can be
obtained this way. When using non-calibration mode, one should
aware that the frequency of R-oscillator may alter due to
manufacturing process variations, supply voltage, operating
temperature and tolerance of external R components used.
5.9. Low Voltage Detection
The SPL61A provides a 2.6V/2.4V voltage detector to detect a low
voltage event. Users can turn on 2.6V detection and read bit1 of
port $24 periodically to monitor if VDD is lower than 2.6V. In
addition, if 2.4V detection is turned on and VDD drops below 2.4V,
after a SLEEP command is issued, system will shut down all
activities(LCD bias, LCD display, 32768 oscillator) and enters
standby to reduce current consumption. This low voltage power
down can be awakened by a PEF0 key change or RESET. Users
can use this feature to implement low battery check/battery
change function.
OPERATING
STANDBY
VDD < 2.4V and SLEEP
Port EF0 Key wake-up
or user reset
State Diagram of Low Voltage Power Down
Sunplus Technology Co., Ltd.
Proprietary & Confidential
6
AUG. 13, 2001
Version: 1.2
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