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SPL11A PROGRAMMING GUIDE
PRELIMINARY
5.3.2
P_10H_IO_Config ($0010).................................................................................................... 18
5.3.3
INB Structure......................................................................................................................... 19
6
SYSTEM CONTROL...................................................................................................................................... 20
6.1
S
YSTEM
C
ONTROL
.................................................................................................................................. 20
6.1.1
P_0FH_SYS_SWITCH ($000F) ............................................................................................ 20
6.1.2
P_0FH_SYS_SWITCH ($000F) ............................................................................................ 21
6.2
R
ESET
F
LAGS
........................................................................................................................................ 22
6.2.1
P_12H_RST_FG ($0012)...................................................................................................... 22
7
TIMER/COUNTER ......................................................................................................................................... 23
7.1
T
IMER
S
TRUCTURE
................................................................................................................................. 23
7.2
T
IMER
S
ETUP
& I
NITIALIZATION
................................................................................................................ 23
7.2.1
P_09H_TIMER_SET ($0009): Set the timer/counter configuration ....................................... 23
7.3
T
IMER
/I
NTERRUPT
C
LOCK
S
OURCES
........................................................................................................ 24
A. HSCK sources for timer, interrupt................................................................................................ 24
7.3.1
P_0CH_TIMER_INT1 ($000C).............................................................................................. 24
B.
LSCK(32768) sources for timer, interrupt sources................................................................... 25
7.3.2
P_0DH_TIMER_INT2 ($000D).............................................................................................. 25
7.4
T
IMER
D
ATA
R
EGISTER
............................................................................................................................ 26
7.4.1
P_0AH_TML_LATCH ($000A)............................................................................................... 26
7.4.2
P_0BH_TMH_LATCH ($000B).............................................................................................. 26
8
LCD................................................................................................................................................................ 27
8.1
LCD RAM
MAPPING
............................................................................................................................... 27
8.2
C
ONTROL REGISTERS
.............................................................................................................................. 27
8.2.1
Port_LCD_CTL ($0004)......................................................................................................... 27
8.2.2
LCD clock control.................................................................................................................. 29
8.3
M
ULTIPLE FUNCTIONS
(I/O,
SEGMENT
&
COMMON SHARING
) ....................................................................... 30
8.3.1
LCD dot & I/O........................................................................................................................ 30
8.3.2
LCD mapping with dot resolution........................................................................................... 31
9
WAKEUP / INTERRUPT ................................................................................................................................ 32
9.1
W
AKEUP
/I
NTERRUPT
S
TRUCTURE
D
IAGRAM
.............................................................................................. 32
9.2
W
AKEUP
/I
NTERRUPT
C
ONTROL REGISTERS
............................................................................................... 33
9.2.1
P_07H_WKU_SET ($0007)................................................................................................... 33
9.2.2
Port_WKU_CLR ($0008)....................................................................................................... 34
Sunplus Technology Co., Ltd.
PAGE 3
V0.1 – OCT. 23, 2002
9.2.3
P_0EH_INT_SET($000E)...................................................................................................... 34